ARM Cortex-A15 MPCore Processor Technical Reference Manual

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Program Trace Macrocell31 7 60ReservedATIDM[6:0]Table 12-20 shows the ITATBID bit assignments.Figure 12-17 ITATBID bit assignmentsTable 12-20 ITATBID bit assignmentsBits Name Function[31:7] - Reserved[6:0] ATIDM[6:0] Drives the ATIDM[6:0] outputs12.7.18 ATB Control Register 0The ITATBCTR0 characteristics are:PurposeControls signal outputs when bit[0] of the ETMITCTRL is set. SeeIntegration Mode Control Register on page 12-30.Usage constraints There are no usage constraints.ConfigurationsAvailable in all PTM configurations.Attributes See the register summary in Table 12-4 on page 12-11.Figure 12-18 shows the ITATBCTR0 bit assignments.31 10 9 8 72 1 0ReservedReservedATBYTESM[1:0]AFREADYMATVALIDMTable 12-21 shows the ITATBCTR0 bit assignments.Figure 12-18 ITATBCTR0 bit assignmentsTable 12-21 ITATBCTR0 bit assignmentsBits Name Function[31:10] - Reserved[9:8] ATBYTESM[1:0] Drives the ATBYTESM outputs[7:2] - Reserved[1] AFREADYM Drives the AFREADYM output[0] ATVALIDM Drives the ATVALIDM outputARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 12-29ID062913Non-Confidential
Program Trace Macrocell12.7.19 Integration Mode Control RegisterThe ETMITCTRL Register enables topology detection and integration testing.When bit[0] is set to 1, the PTM enters an integration mode. On reset this bit is cleared to 0.Before entering integration mode, the PTM must be powered up and in programming mode.This means bit[0] of the Main Control Register is set to 0, and bit[10] of the Main ControlRegister is set to 1. See Main Control Register on page 12-14.After leaving integration mode, the PTM must be reset before attempting to perform tracing.The CoreSight Program Trace Flow Architecture Specification describes the operation of thisregister in the PTM.12.7.20 Peripheral Identification RegistersThe Peripheral Identification Registers provide standard information required for all CoreSightcomponents. They are a set of eight registers, listed in register number order in Table 12-22.Table 12-22 Summary of the Peripheral ID RegistersRegister Value OffsetPeripheral ID4 0x04 0xFD0Peripheral ID5 0x00 0xFD4Peripheral ID6 0x00 0xFD8Peripheral ID7 0x00 0xFDCPeripheral ID0 0x5F 0xFE0Peripheral ID1 0xB9 0xFE4Peripheral ID2 0x3B 0xFE8Peripheral ID3 0x00 0xFECOnly bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, theeight Peripheral ID Registers define a single 64-bit Peripheral ID.The CoreSight Program Trace Flow Architecture Specification describes these registers.12.7.21 Component Identification RegistersThere are four read-only Component Identification Registers, Component ID0 to ComponentID3. Table 12-23 shows these registers.Table 12-23 Summary of the Component Identification RegistersRegister Value OffsetComponent ID0 0x0D 0xFF0Component ID1 0x90 0xFF4Component ID2 0x05 0xFF8Component ID3 0xB1 0xFFCARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 12-30ID062913Non-Confidential
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®ARM®Cortex -A15 MPCoreProcessorR
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ContentsARM Cortex-A15 MPCore Proce
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Contents11.4 PMU register descripti
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PrefaceAbout this bookThis book is
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Preface(continued)Stylemonospace bo
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the Cortex-A1
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Introduction1.2.3 Debug architectur
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Introduction1.4 InterfacesThe proce
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Introduction• The L2 tag RAM regi
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IntroductionThe ARM product deliver
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Introduction1.7.5 r1p0 - r2p0The fo
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Introduction• Added L1 data TLB s
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Functional Description2.1 About the
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Functional DescriptionLoad/Store un
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Functional Description2.2 Interface
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Functional Description2.3 Clocking
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Functional DescriptionFigure 2-5 sh
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Functional DescriptionAll resets ar
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Functional DescriptionPowerup reset
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Functional Description• nPRESETDB
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Functional Description• L2 unifie
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Functional DescriptionOn entry into
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Functional DescriptionWhen the proc
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Functional DescriptionNoteFigure 2-
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Functional DescriptionRegional cloc
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Functional DescriptionTable 2-3 Val
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Functional Description4. Release th
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Functional DescriptionDebug power d
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Functional DescriptionNoteAfter a p
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Functional DescriptionThe external
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Programmers Model3.1 About the prog
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Programmers Model3.3 Advanced SIMD
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Programmers ModelYou can use the CP
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Programmers Model3.6 Large Physical
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Programmers Model3.8 Modes of opera
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Chapter 4System ControlThis chapter
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System Control4.2 Register summaryT
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System ControlOp1 CRm Op2 Name Rese
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System ControlTable 4-6 c5 register
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System ControlTable 4-8 c7 register
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System ControlTable 4-10 c9 registe
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System Control4.2.14 c15 registersT
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System ControlName CRn Op1 CRm Op2
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System Control4.2.19 Other system c
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System Control4.2.24 Performance mo
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System Control4.2.26 Virtualization
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System Control4.3 Register descript
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System ControlTo access the CTR, re
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System ControlTable 4-34 shows the
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System Control4.3.12 Memory Model F
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System ControlTable 4-40 ID_MMFR3 b
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System Control31 28 27 24 23 20 19
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System ControlTable 4-43 ID_ISAR2 b
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System ControlConfigurationsAvailab
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System ControlMCR p15, 4, , c0, c0,
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System ControlTable 4-52 SCTLR bit
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System Control31 30 29 28 27 26 25
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System ControlTable 4-53 ACTLR bit
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System ControlTable 4-53 ACTLR bit
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System ControlUsage constraints The
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System Control• The L2 internal a
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System Control31 30 29 28 27 26 25
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System ControlUsage constraints The
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System ControlTable 4-59 HCPTR bit
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System ControlTable 4-61 DFSR bit a
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System ControlTable 4-63 IFSR bit a
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System ControlConfigurationsAvailab
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System Control• UNKNOWN when exec
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System Control31 30 26 25 24 23 22
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System Control• Only accessible f
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System Control31 0DataFigure 4-40 I
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System ControlThe data returned fro
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System ControlThe data returned fro
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System Control31 24 23 21 20 19 18
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System Control4.3.60 L2 Auxiliary C
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System ControlTable 4-74 L2ACTLR bi
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System Control• Is only accessibl
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System ControlTable 4-79 L2MERRSR b
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Memory Management Unit5.1 About the
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Memory Management Unit5.3 TLB match
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Memory Management Unit• The TLB t
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Memory Management Unit5.6 Intermedi
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Memory Management Unit5.7 External
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Level 1 Memory System6.1 About the
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Level 1 Memory System6.3 L1 instruc
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Level 1 Memory System6.4 L1 data me
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Level 1 Memory SystemL1 or L2 cache
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Level 1 Memory SystemExternal globa
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Level 1 Memory System6.5 Program fl
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Level 1 Memory SystemReset:• Disa
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Chapter 7Level 2 Memory SystemThis
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Level 2 Memory System7.2 Cache orga
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Level 2 Memory System7.2.5 Register
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Level 2 Memory SystemNote• The L2
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Level 2 Memory System7.4 L2 cache p
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Level 2 Memory System7.6 Asynchrono
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Level 2 Memory SystemFor certain tr
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Level 2 Memory System7.7.6 Snoop fi
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Level 2 Memory SystemTable 7-6 show
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Chapter 8Generic Interrupt Controll
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Generic Interrupt Controller8.2 GIC
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Generic Interrupt Controller8.2.4 I
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Generic Interrupt Controller8.3 GIC
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Generic Interrupt ControllerOffset
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Generic Interrupt ControllerTable 8
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Generic Interrupt ControllerPrivate
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Generic Interrupt Controller0x1D043
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Generic Interrupt ControllerThe Cor
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Generic Interrupt ControllerTable 8
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Generic Interrupt Controller8.3.8 V
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Generic Timer9.1 About the Generic
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Generic Timer9.3 Generic Timer prog
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Chapter 10DebugThis chapter describ
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Debug• Operating systems.• Hard
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DebugnPRESETDBGThis signal initiali
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DebugTable 10-1 CP14 debug register
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DebugTable 10-1 CP14 debug register
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DebugTable 10-2 DBGDIDR bit assignm
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DebugTable 10-4 shows the DBGDRCR b
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DebugConfigurationsAttributesThe pr
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DebugTable 10-8 DBGBCR bit assignme
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DebugTable 10-10 shows the DBGWCR b
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Debug31 12 11 2 1 0ROMADDR[31:12]Re
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Debug10.4.12 OS Lock Status Registe
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DebugTable 10-15 shows the DBGPRCR
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DebugTable 10-16 DBGDSAR bit assign
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Debug31 1 0ReservedIntegration mode
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DebugTable 10-22 shows the DBGDEVID
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Debug10.4.23 Component Identificati
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Page 292 and 293: Performance Monitor Unit11.1 About
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Page 296 and 297: Performance Monitor UnitTable 11-1
Page 304 and 305: Performance Monitor Unit11.5 Effect
Page 308 and 309: Performance Monitor Unit11.7 Interr
Page 310 and 311: Chapter 12Program Trace MacrocellTh
Page 312 and 313: Program Trace Macrocell12.2 PTM opt
Page 314 and 315: Program Trace MacrocellYou can also
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Page 318 and 319: Program Trace Macrocellarchitecture
Page 320 and 321: Program Trace Macrocell12.6 Registe
Page 322 and 323: Program Trace MacrocellTable 12-4 P
Page 324 and 325: Program Trace MacrocellTable 12-5 E
Page 326 and 327: Program Trace MacrocellTable 12-6 E
Page 328 and 329: Program Trace Macrocell31 26 25 24
Page 330 and 331: Program Trace Macrocell12.7.8 Confi
Page 332 and 333: Program Trace Macrocell12.7.10 Auxi
Page 334 and 335: Program Trace Macrocell31 4 3 2 0Re
Page 336 and 337: Program Trace MacrocellTable 12-17
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Page 342 and 343: Cross Trigger13.1 About the cross t
Page 344 and 345: Cross Trigger13.3 Cortex-A15 CTIIn
Page 346 and 347: Chapter 14NEON and VFP UnitThis cha
Page 348 and 349: NEON and VFP UnitARM DDI 0438I Copy
Page 350 and 351: NEON and VFP UnitSee the ARM ® Arc
Page 352 and 353: NEON and VFP UnitConfigurationsAvai
Page 354 and 355: NEON and VFP UnitTable 14-5 FPSCR b
Page 356 and 357: NEON and VFP UnitTable 14-6 MVFR1 b
Page 358 and 359: NEON and VFP Unit31 30 29 0Reserved
Page 360 and 361: Signal DescriptionsA.1 About the si
Page 362 and 363: Signal DescriptionsA.3 Reset signal
Page 364 and 365: Signal DescriptionsA.5 Generic Inte
Page 366 and 367: Signal DescriptionsA.6 Generic Time
Page 368 and 369: Signal DescriptionsA.8 Power manage
Page 370 and 371: Signal DescriptionsA.9 AXI interfac
Page 372 and 373: Signal DescriptionsWrite address ch
Page 374 and 375: Signal DescriptionsTable A-14 Read
Page 376 and 377: Signal DescriptionsTable A-20 Write
Page 378 and 379: Signal DescriptionsA.10 External de
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Page 382 and 383: Signal DescriptionsA.12 Cross trigg
Page 384 and 385: Signal DescriptionsA.14 DFT and MBI
Page 386 and 387: Appendix BRevisionsThis appendix de
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RevisionsTable B-3 Differences betw
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ARM Cortex-A15 MPCore Processor Technical Reference Manual

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