ARM Cortex-A15 MPCore Processor Technical Reference Manual

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System ControlTable 4-53 ACTLR bit assignments (continued)Bits Name Function[2] a Limit to one loop buffer detect perflushLimits to one loop buffer detect per flush:0 Normal behavior. This is the reset value.1 Limits to one loop buffer detect per flush.[1] a Disable loop buffer Disables loop buffer:0 Enables loop buffer. This is the reset value.1 Disables loop buffer.[0] a Enable invalidates of BTB Enables invalidate of BTB:0 The CP15 Invalidate Instruction Cache All and InvalidateInstruction Cache by MVA instructions only invalidates theinstruction cache array. This is the reset value.1 The CP15 Invalidate Instruction Cache All and InvalidateInstruction Cache by MVA instructions invalidates theinstruction cache array and branch target buffer.a. This bit is provided for debugging and characterization purpose only. For normal operation, ARM recommends that you do not change thevalue of this bit from its reset value.To access the ACTLR, read or write the CP15 register with:MRC p15, 0, , c1, c0, 1 ; Read Auxiliary Control RegisterMCR p15, 0, , c1, c0, 1 ; Write Auxiliary Control Register4.3.29 Coprocessor Access Control RegisterThe CPACR characteristics are:PurposeControls access to coprocessors CP10 and CP11.Usage constraints The CPACR:• Is a read/write register.• Is Common to the Secure and Non-secure states.• Is only accessible from PL1 or higher.• Has no effect on instructions executed in Hyp mode.ConfigurationsBits in the NSACR, see Non-Secure Access Control Register onpage 4-65, control Non-secure access to the CPACR fields.Attributes See the register summary in Table 4-3 on page 4-5.Figure 4-25 shows the CPACR bit assignments.31 3024 23 22 21 20 19 0Reserved cp11 cp10 ReservedASEDISFigure 4-25 CPACR bit assignmentsARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-62ID062913Non-Confidential
System ControlTable 4-54 shows the CPACR bit assignments.Table 4-54 CPACR bit assignmentsBits Name Function[31] ASEDIS Disable Advanced SIMD Extension functionality:0 All Advanced SIMD and VFP instructions execute normally.1 All Advanced SIMD instructions that are not VFP instructions are UNDEFINEDwhen accessed from PL1 and Pl0 modes.If VFP is implemented and NEON is not implemented, this bit is RAO/WI.If VFP and NEON are not implemented, this bit is UNK/SBZP.[30] - Reserved, RAZ/WI.[29:28] - Reserved, UNK/SBZP.[27:24] - Reserved, RAZ/WI.[23:22] cp11 Defines the access rights for coprocessor 11:b00Access denied. Any attempt to access the coprocessor generates an UndefinedInstruction exception. This is the reset value.b01Access at PL1 or higher only. Any attempt to access the coprocessor fromsoftware executing at PL0 generates an Undefined Instruction exception.b10Reserved. The effect of this value is UNPREDICTABLE.b11 Full access. The meaning of full access is defined by coprocessor 11.If VFP and NEON are not implemented, this field is RAZ/WI.[21:20] cp10 Defines the access rights for coprocessor 10:b00Access denied. Any attempt to access the coprocessor generates an UndefinedInstruction exception. This is the reset value.b01Access at PL1 or higher only. Any attempt to access the coprocessor fromsoftware executing at PL0 generates an Undefined Instruction exception.b10Reserved. The effect of this value is UNPREDICTABLE.[19:0] - Reserved, RAZ/WI.b11 Full access. The meaning of full access is defined by coprocessor 10.If VFP and NEON are not implemented, this field is RAZ/WI.NoteIf the values of the cp11 and cp10 fields are not the same, the behavior is UNPREDICTABLE.To access the CPACR, read or write the CP15 register with:MRC p15, 0, , c1, c0, 2; Read Coprocessor Access Control RegisterMCR p15, 0, , c1, c0, 2; Write Coprocessor Access Control Register4.3.30 Secure Configuration RegisterThe SCR characteristics are:PurposeDefines the configuration of the current security state. It specifies:• The security state of the processor, Secure or Non-secure.• What mode the processor branches to, if an IRQ, FIQ or externalabort occurs.• Whether the CPSR.F and CPSR.A bits can be modified whenSCR.NS is 1.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-63ID062913Non-Confidential
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®ARM®Cortex -A15 MPCoreProcessorR
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ContentsARM Cortex-A15 MPCore Proce
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Contents11.4 PMU register descripti
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PrefaceAbout this bookThis book is
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Preface(continued)Stylemonospace bo
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the Cortex-A1
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Introduction1.2.3 Debug architectur
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Introduction1.4 InterfacesThe proce
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Introduction• The L2 tag RAM regi
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IntroductionThe ARM product deliver
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Introduction1.7.5 r1p0 - r2p0The fo
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Introduction• Added L1 data TLB s
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Functional Description2.1 About the
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Functional DescriptionLoad/Store un
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Functional Description2.2 Interface
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Functional Description2.3 Clocking
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Functional DescriptionFigure 2-5 sh
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Functional DescriptionAll resets ar
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Functional DescriptionPowerup reset
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Functional Description• nPRESETDB
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Functional Description• L2 unifie
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Functional DescriptionOn entry into
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Functional DescriptionWhen the proc
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Functional DescriptionNoteFigure 2-
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Functional DescriptionRegional cloc
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Functional DescriptionTable 2-3 Val
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Functional Description4. Release th
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Functional DescriptionDebug power d
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Functional DescriptionNoteAfter a p
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Functional DescriptionThe external
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Programmers Model3.1 About the prog
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Programmers Model3.3 Advanced SIMD
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Programmers ModelYou can use the CP
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Programmers Model3.6 Large Physical
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Programmers Model3.8 Modes of opera
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Chapter 4System ControlThis chapter
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System Control4.2 Register summaryT
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System ControlOp1 CRm Op2 Name Rese
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System ControlTable 4-6 c5 register
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System ControlTable 4-8 c7 register
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Page 89 and 90: System ControlName CRn Op1 CRm Op2
Page 91 and 92: System Control4.2.19 Other system c
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Page 97 and 98: System Control4.2.26 Virtualization
Page 101 and 102: System Control4.3 Register descript
Page 103 and 104: System ControlTo access the CTR, re
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Page 110 and 111: System Control4.3.12 Memory Model F
Page 114 and 115: System ControlTable 4-40 ID_MMFR3 b
Page 116 and 117: System Control31 28 27 24 23 20 19
Page 118 and 119: System ControlTable 4-43 ID_ISAR2 b
Page 126 and 127: System ControlConfigurationsAvailab
Page 128 and 129: System ControlMCR p15, 4, , c0, c0,
Page 130 and 131: System ControlTable 4-52 SCTLR bit
Page 134 and 135: System ControlTable 4-53 ACTLR bit
Page 138 and 139: System ControlUsage constraints The
Page 140 and 141: System Control• The L2 internal a
Page 146 and 147: System ControlUsage constraints The
Page 148 and 149: System ControlTable 4-59 HCPTR bit
Page 152 and 153: System ControlTable 4-61 DFSR bit a
Page 154 and 155: System ControlTable 4-63 IFSR bit a
Page 156 and 157: System ControlConfigurationsAvailab
Page 158 and 159: System Control• UNKNOWN when exec
Page 162 and 163: System Control• Only accessible f
Page 164 and 165: System Control31 0DataFigure 4-40 I
Page 168 and 169: System ControlThe data returned fro
Page 170 and 171: System ControlThe data returned fro
Page 174 and 175: System Control4.3.60 L2 Auxiliary C
Page 176 and 177: System ControlTable 4-74 L2ACTLR bi
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Page 184 and 185: System ControlTable 4-79 L2MERRSR b
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Memory Management Unit5.1 About the
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Memory Management Unit5.3 TLB match
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Memory Management Unit• The TLB t
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Memory Management Unit5.6 Intermedi
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Memory Management Unit5.7 External
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Level 1 Memory System6.1 About the
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Level 1 Memory System6.3 L1 instruc
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Level 1 Memory System6.4 L1 data me
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Level 1 Memory SystemL1 or L2 cache
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Level 1 Memory SystemExternal globa
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Level 1 Memory System6.5 Program fl
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Level 1 Memory SystemReset:• Disa
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Chapter 7Level 2 Memory SystemThis
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Level 2 Memory System7.2 Cache orga
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Level 2 Memory System7.2.5 Register
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Level 2 Memory SystemNote• The L2
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Level 2 Memory System7.4 L2 cache p
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Level 2 Memory System7.6 Asynchrono
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Level 2 Memory SystemFor certain tr
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Level 2 Memory System7.7.6 Snoop fi
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Level 2 Memory SystemTable 7-6 show
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Chapter 8Generic Interrupt Controll
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Generic Interrupt Controller8.2 GIC
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Generic Interrupt Controller8.2.4 I
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Generic Interrupt Controller8.3 GIC
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Generic Interrupt ControllerOffset
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Generic Interrupt ControllerTable 8
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Generic Interrupt ControllerPrivate
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Generic Interrupt Controller0x1D043
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Generic Interrupt ControllerThe Cor
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Generic Interrupt ControllerTable 8
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Generic Interrupt Controller8.3.8 V
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Generic Timer9.1 About the Generic
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Generic Timer9.3 Generic Timer prog
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Chapter 10DebugThis chapter describ
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Debug• Operating systems.• Hard
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DebugnPRESETDBGThis signal initiali
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DebugTable 10-1 CP14 debug register
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DebugTable 10-1 CP14 debug register
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DebugTable 10-2 DBGDIDR bit assignm
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DebugTable 10-4 shows the DBGDRCR b
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DebugConfigurationsAttributesThe pr
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DebugTable 10-8 DBGBCR bit assignme
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DebugTable 10-10 shows the DBGWCR b
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Debug31 12 11 2 1 0ROMADDR[31:12]Re
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Debug10.4.12 OS Lock Status Registe
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DebugTable 10-15 shows the DBGPRCR
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DebugTable 10-16 DBGDSAR bit assign
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Debug31 1 0ReservedIntegration mode
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DebugTable 10-22 shows the DBGDEVID
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Debug10.4.23 Component Identificati
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Debug10.6 External debug interfaceT
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DebugIf software running on the pro
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Performance Monitor Unit11.1 About
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Performance Monitor Unit11.3 PMU re
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Performance Monitor UnitTable 11-1
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Performance Monitor Unit11.5 Effect
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Performance Monitor Unit11.7 Interr
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Chapter 12Program Trace MacrocellTh
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Program Trace Macrocell12.2 PTM opt
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Program Trace MacrocellYou can also
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Program Trace Macrocell12.5 PTM pro
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Program Trace Macrocellarchitecture
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Program Trace Macrocell12.6 Registe
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Program Trace MacrocellTable 12-4 P
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Program Trace MacrocellTable 12-5 E
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Program Trace MacrocellTable 12-6 E
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Program Trace Macrocell31 26 25 24
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Program Trace Macrocell12.7.8 Confi
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Program Trace Macrocell12.7.10 Auxi
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Program Trace Macrocell31 4 3 2 0Re
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Program Trace MacrocellTable 12-17
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Program Trace Macrocell31 7 60Reser
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Program Trace MacrocellThe Componen
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Cross Trigger13.1 About the cross t
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Cross Trigger13.3 Cortex-A15 CTIIn
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Chapter 14NEON and VFP UnitThis cha
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NEON and VFP UnitARM DDI 0438I Copy
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NEON and VFP UnitSee the ARM ® Arc
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NEON and VFP UnitConfigurationsAvai
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NEON and VFP UnitTable 14-5 FPSCR b
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NEON and VFP UnitTable 14-6 MVFR1 b
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NEON and VFP Unit31 30 29 0Reserved
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Signal DescriptionsA.1 About the si
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Signal DescriptionsA.3 Reset signal
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Signal DescriptionsA.5 Generic Inte
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Signal DescriptionsA.6 Generic Time
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Signal DescriptionsA.8 Power manage
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Signal DescriptionsA.9 AXI interfac
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Signal DescriptionsWrite address ch
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Signal DescriptionsTable A-14 Read
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Signal DescriptionsTable A-20 Write
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Signal DescriptionsA.10 External de
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Signal DescriptionsTable A-27 Misce
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Signal DescriptionsA.12 Cross trigg
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Signal DescriptionsA.14 DFT and MBI
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Appendix BRevisionsThis appendix de
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RevisionsTable B-3 Differences betw
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