ARM Cortex-A15 MPCore Processor Technical Reference Manual

DebugConfigurationsThe processor implements 2 BRPs that can be used for VMID matching,and is specified by the DBGDIDR.CTX_CMPs field, see Debug IDRegister on page 10-10.Attributes See the register summary in Table 10-1 on page 10-6.Figure 10-12 shows the DBGBXVR bit assignments.31 8 70UNK/SBZPVMIDTable 10-12 shows the DBGBXVR bit assignments.Bits Name Function[31:8] - UNK/SBZP.Figure 10-12 DBGBXVR bit assignmentsTable 10-12 DBGBXVR bit assignments[7:0] VMID VMID value. Compared VTTBR.VMID, the Virtual Machine ID (VMID) field. The debug logicgenerates a debug event when an instruction that matches the breakpoint is committed forexecution. See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition formore information.10.4.11 OS Lock Access RegisterThe DBGOSLAR characteristics are:PurposeProvides a lock for the debug registers. The OS Lock also disablesSoftware debug events.Usage constraints Use DBGOSLSR to check the current status of the lock, see OS LockStatus Register on page 10-23.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 10-1 on page 10-6.Figure 10-13 shows the DBGOSLAR bit assignments.31 0OS Lock AccessBits Name FunctionTable 10-13 shows the DBGOSLAR bit assignments.Figure 10-13 DBGOSLAR bit assignmentsTable 10-13 DBGOSLAR bit assignments[31:0] OS Lock Access Writing the key value 0xC5ACCE55 to this field locks the debug registers.Writing any other value to this register unlocks the debug registers if they are locked. See theARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for more information.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 10-22ID062913Non-Confidential