ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-56 NSACR bit assignments (continued)Bits Name Function[15] NSASEDIS Disable Non-secure Advanced SIMD functionality:0 This bit has no effect on the ability to write to CPACR.ASEDIS. This is the resetvalue.1 When executing in Non-secure state, CPACR.ASEDIS is RAO/WI.If VFP is implemented and NEON is not implemented, this bit is RAO/WI.If VFP and NEON are not implemented, this bit is UNK/SBZP.[14:12] - Reserved, RAZ/WI.[11] cp11 Non-secure access to coprocessor 11 enable:0 Secure access only. Any attempt to access coprocessor 11 in Non-secure stateresults in an Undefined Instruction exception. If the processor is in Non-securestate, the corresponding bits in the CPACR ignore writes and read as 0b00, accessdenied. This is the reset value.1 Secure or Non-secure access.If VFP and NEON are not implemented, this bit is RAZ/WI.[10] cp10 Non-secure access to coprocessor 10 enable:0 Secure access only. Any attempt to access coprocessor 10 in Non-secure stateresults in an Undefined Instruction exception. If the processor is in Non-securestate, the corresponding bits in the CPACR ignore writes and read as 0b00, accessdenied. This is the reset value.1 Secure or Non-secure access.If VFP and NEON are not implemented, this bit is RAZ/WI.[9:0] - Reserved, RAZ/WI.NoteIf the values of the cp11 and cp10 fields are not the same, the behavior is UNPREDICTABLE.To access the NSACR, read or write the CP15 register with:MRC p15, 0, , c1, c1, 2 ; Read Non-Secure Access Control Register dataMCR p15, 0, , c1, c1, 2 ; Write Non-Secure Access Control Register data4.3.32 Hyp System Control RegisterThe HSCTLR characteristics are:PurposeProvides the top level control of the system operation in Hyp mode. Thisregister provides Hyp mode control of a subset of the features controlledby the SCTLR bits. See System Control Register on page 4-54.Usage constraints The HSCTLR is:• A read/write register.• Only accessible from Hyp mode or from Monitor mode whenSCR.NS is 1.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-3 on page 4-5.Figure 4-28 on page 4-68 shows the HSCTLR bit assignments.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-67ID062913Non-Confidential