ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlThe data returned from accessing L1-I BTB RAM are:IL1DATA2 BTB data[77:64].IL1DATA1 BTB data[63:32].IL1DATA0 BTB data[31:0].Figure 4-46 shows the RAMINDEX bit assignments for accessing L1-I GHB RAM.31 24 23 14 13 4 3 0RAMID = 0x03ReservedIndex [13:4]ReservedFigure 4-46 RAMINDEX bit assignments for L1-I GHB RAMThe RAMINDEX address bits for accessing L1-I GHB RAM are:Index[13:5] Row select.Index[4]Bank select.The data returned from accessing L1-I GHB RAM are:IL1DATA2 32'b0.IL1DATA1 GHB data[47:32].IL1DATA0 GHB data[31:0].Figure 4-47 shows the RAMINDEX bit assignments for accessing L1-I TLB array.31 24 23 5 40RAMID = 0x04ReservedTLB entryFigure 4-47 RAMINDEX bit assignments for L1-I TLB arrayThe RAMINDEX address bits for accessing L1-I TLB array are:TLB entrySelects one of the 32 entries.The data returned from accessing L1-I TLB array are:IL1DATA2 TLB entry data[95:64].IL1DATA1 TLB entry data[63:32].IL1DATA0 TLB entry data[31:0].Figure 4-48 shows the RAMINDEX bit assignments for accessing L1-I indirect predictor RAM.31 24 23 8 70RAMID = 0x05 Reserved Index [7:0]Figure 4-48 RAMINDEX bit assignments for L1-I indirect predictor RAMThe RAMINDEX address bits for accessing L1-I indirect predictor RAM are:Index[7:0]Indirect predictor entry.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-94ID062913Non-Confidential