ARM Cortex-A15 MPCore Processor Technical Reference Manual

Program Trace Macrocell12.6 Register summaryThis section summarizes the PTM registers. For full descriptions of the PTM registers, see:• Register descriptions on page 12-14, for the implementation-defined registers.• The CoreSight Program Flow Trace Architecture Specification, for the other registers.Note• Registers not listed here are not implemented. Reading a non-implemented registeraddress returns 0. Writing to a non-implemented register address has no effect.• In Table 12-4, access type is described as follows:RW Read and write.RO Read only.WO Write only.All PTM registers are 32 bits wide. The PTM registers are defined in the CoreSight ProgramFlow Trace Architecture Specification. Table 12-4 lists all of the registers that are implementedin the PTM with their offsets from a base address. This base address is defined by the systemintegrator when placing the PTM in the Debug APB memory map.Base offset Function Type DescriptionPTM configuration0x000 Main Control RW Main Control Register on page 12-140x004 Configuration Code RO Configuration Code Register on page 12-16Table 12-4 PTM register summary0x008 Trigger Event RW CoreSight Program Flow Trace Architecture Specification0x010 Status RW CoreSight Program Flow Trace Architecture Specification0x014 System Configuration RO System Configuration Register on page 12-17TraceEnable control0x018 TraceEnable Start/Stop Control RW TraceEnable Start/Stop Control Register on page 12-180x020 TraceEnable Event RW CoreSight Program Flow Trace Architecture Specification0x024 TraceEnable Control RW TraceEnable Control Register 1 on page 12-18Address comparators0x040-0x05C Address Comparator Value 1- 8 RW CoreSight Program Flow Trace Architecture Specification0x080-0x09C Address Comparator Access Type 1- 8 RWCounters0x140-0x144 Counter Reload Value 1-2 RW CoreSight Program Flow Trace Architecture Specification0x150-0x154 Counter Enable 1-2 RW0x160-0x164 Counter Reload Event 1-2 RW0x170-0x174 Counter Value 1-2 RWSequencer registersARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 12-11ID062913Non-Confidential