ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 1 Memory System6.4 L1 data memory systemThe L1 data memory system executes all memory operations in the Cortex-A15 MPCoreprocessor. In addition, it handles cache maintenance operations, TLB maintenance operations,and exclusive operations using the Load-Exclusive, Store-Exclusive and Clear-Exclusiveinstructions.The L1 memory system supports out-of-order execution of instructions. Loads can be executedand return their data while they are still speculative and might be flushed. Stores can beexecuted, but not committed to memory, while they are still speculative. Speculative loads canforward data from older speculative stores.The L1 memory system is non-blocking and supports hit-under-miss. For Normal memory, upto six 64-byte cache line requests can be outstanding at a time. While those requests are waitingfor memory, loads to different cache lines can hit the cache and return their data, and stores todifferent cache lines can hit and update the cache.The L1 data memory system includes the following:• L1 data cache.• Address generation logic.• The L1 TLBs.• Buffering for stores that have not been written to the cache or memory.• Fill buffers for processing cache line fills and non-cacheable reads.• Coherence logic for handling snoop requests.This section describes L1 data memory system in:• Behavior for different memory types.• Coherence on page 6-8.• Cache disabled behavior on page 6-9.• Non-cacheable streaming enhancement on page 6-9.• Synchronization primitives on page 6-9.• LDRT and STRT instructions on page 6-10.• Preload instruction behavior on page 6-10.• Error Correction Code on page 6-11.6.4.1 Behavior for different memory typesThe L1 data memory system uses memory attributes from the MMU to determine the behaviorfor memory transactions to regions of memory. See Chapter 5 Memory Management Unit formore information.The L1 data memory system uses the following memory types:• Write-Back Read-Write-Allocate on page 6-7.• Write-Back No-Allocate on page 6-7.• Write-Through on page 6-8.• Non-Cacheable on page 6-8.• Strongly-ordered and Device on page 6-8.NoteSome attribute combinations are only available if the LPAE page table format is used.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 6-6ID062913Non-Confidential