ARM Cortex-A15 MPCore Processor Technical Reference Manual

Functional Description4. Release the processor output clamps by deasserting nISOLATECPU. Be sure to keepnISOLATECX asserted.5. Continue a normal powerup reset sequence while nISOLATECX remain asserted.NEON and VFP power domainIf the NEON and VFP unit is not required, you can reduce leakage power by turning off thepower to the unit. While the unit is powered down, any Advanced SIMD or VFP instructionsexecuted take the Undefined Instruction exception.To enable the NEON and VFP unit to be powered down, the implementation must place the uniton a separately controlled power supply. In addition, you must clamp the outputs of the NEONand VFP unit to benign values while the unit is powered down, to indicate that the unit is idle.To power down the NEON and VFP power domain while the processor is in reset, apply thefollowing sequence:1. Assert nCPUPORESET for powerup reset or nCORERESET for soft reset.2. Activate the NEON and VFP unit output clamps by asserting the nISOLATECX inputLOW.3. Remove power from the NEON and VFP power domain. If the processor is executing apowerup reset sequence or is first powering up, keep the NEON and VFP power domainoff while applying power to the other power domains.4. Complete and exit the reset sequence.NoteIf the NEON and VFP output clamps are released without following one of the specified NEONand VFP powerup sequences, the results are UNPREDICTABLE.To power down the NEON and VFP power domain while the processor is not in reset, apply thefollowing sequence:1. You must disable access to the NEON and VFP unit by setting the CPACR and HCPTR.See Coprocessor Access Control Register on page 4-62 and Hyp Coprocessor TrapRegister on page 4-71. All outstanding Advanced SIMD and VFP instructions retire andall subsequent Advanced SIMD and VFP instructions cause an Undefined Instructionexception.MRC P15, 0, , c1, c0, 2; Read CPACRBIC , , #0x00F00000; Clear CP10 and CP11 bitsMCR p15, 0, , c1, c0, 2; Write CPACRMRC p15, 4, , c1, c1, 2; Read HCPTRORR , , #0x00000C00; Set TCP10 and TCP11 bitsMCR p15, 4, , c1, c1, 2; Write HCPTR2. Execute an ISB instruction to ensure that all of the CP15 register changes in step 1 havebeen committed.3. Software must signal to the external SoC that the NEON and VFP unit is disabled.4. Activate the NEON and VFP output clamps by asserting the nISOLATECX input LOW.5. Remove power from the NEON and VFP power domain.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 2-32ID062913Non-Confidential