ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 1 Memory SystemTable 6-1 shows the memory attribute combinations available.Table 6-1 Memory attribute combinationsMemory type Cacheability Allocation policy Cortex-A15 MPCore processor behaviorStrongly-ordered - - Strongly-orderedDevice - - DeviceNormal Non-Cacheable - Normal Non-CacheableNormal Write-Through Read-Allocate Write-Through No-AllocateNormal Write-Through Write-Allocate Write-Through No-AllocateNormal Write-Through Read-Write-Allocate Write-Through No-ALlocateNormal Write-Through No-Allocate Write-Through AllocateNormal Write-Back Read-Allocate Write-Back Read-Write-AllocateNormal Write-Back Write-Allocate Write-Back Read-Write-AllocateNormal Write-Back Read-Write-Allocate Write-Back Read-Write-AllocateNormal Write-Back No-Allocate Write-Back No-AllocateThe L1 and L2 data memory system uses the inner memory attributes from the MMU todetermine its behavior.If any memory instruction crosses a 4KB page boundary between two pages with differentmemory types such as Normal or Strongly-ordered, the result is UNPREDICTABLE and an abortmight be triggered or incorrect data delivered.If any given physical address is mapped to virtual addresses with different memory types ordifferent cacheability such as Non-Cacheable, Write-Through, or Write-Back, the result isUNPREDICTABLE. This can occur if two virtual addresses are mapped to the same physicaladdress at the same time with different memory type or cacheability, or if the same virtualaddress has its memory type or cacheability changed over time without the appropriate cachecleaning or barriers.Write-Back Read-Write-AllocateThis is expected to be the most common and highest performance memory type. Any read orwrite to this memory type searches the cache to determine if the line is resident. If it is, the lineis read or updated. A store that hits a Write-Back cache line does not update main memory.If the required cache line is not in the cache, one or more cache lines is requested from the L2cache. The L2 cache can obtain the lines from its cache, from another coherent L1 cache, orfrom memory. The line is then placed in the L1 cache, and the operation completes from the L1cache.Write-Back No-AllocateUse Write-Back No-Allocate memory to access data that might be in the cache because othervirtual pages that are mapped to the same physical address are Write-Back Read-Write-Allocate.Write-Back No-Allocate memory is used to avoid polluting the caches when accessing largememory structures that are used only one time. The cache is searched and the correct data isdelivered or updated if the data resides in one of the caches. However, if the request misses theARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 6-7ID062913Non-Confidential