ARM Cortex-A15 MPCore Processor Technical Reference Manual

Program Trace MacrocellTable 12-4 PTM register summary (continued)Base offset Function Type Description0x180-0x194 Sequencer State Transition Event 1-6 RW CoreSight Program Flow Trace Architecture Specification0x19C Current Sequencer State RW CoreSight Program Flow Trace Architecture SpecificationExternal output event0x1A0-0x1A4 External Output Event 1-2 RW CoreSight Program Flow Trace Architecture SpecificationContext ID comparators0x1B0 Context ID Comparator Value 1 RW CoreSight Program Flow Trace Architecture Specification0x1BC Context ID Comparator Mask RW CoreSight Program Flow Trace Architecture SpecificationGeneral control0x1E0 Synchronization Frequency RW Synchronization Frequency Register on page 12-190x1E4 ID RO See ETM ID Register on page 12-200x1E8 Configuration Code Extension RO Configuration Code Extension Register on page 12-210x1EC Extended External Input Selection RW Extended External Input Selection Register on page 12-220x1F8 Timestamp Event RW CoreSight Program Flow Trace Architecture Specification0x1FC Auxiliary Control Register RW Auxiliary Control Register on page 12-230x200 CoreSight Trace ID RW CoreSight Program Flow Trace Architecture Specification0x204 VMID Comparator value RW CoreSight Program Flow Trace Architecture Specification0x300 OS Lock Access Specification WO CoreSight Program Flow Trace Architecture Specification0x304 OS Lock Status RO CoreSight Program Flow Trace Architecture Specification0x310 Power Down Control RW Power Down Control Register on page 12-240x314 Power Down Status RO CoreSight Program Flow Trace Architecture SpecificationIntegration registers0xEDC Miscellaneous Outputs WO Miscellaneous Output Register on page 12-250xEE0 Miscellaneous Inputs RO Miscellaneous Input Register on page 12-260xEE8 Trigger WO Trigger Register on page 12-260xEEC ATB Data 0 WO ITATBDATA0 bit assignments on page 12-270xEF0 ATB Control 2 RO ATB Control Register 2 on page 12-280xEF4 ATB Identification WO ATB Identification Register on page 12-280xEF8 ATB Control 0 WO ATB Control Register 0 on page 12-290xF00 Integration Mode Control RW Integration Mode Control Register on page 12-300xFA0 Claim Tag Set RW CoreSight Program Flow Trace Architecture Specification0xFA4 Claim Tag Clear RW CoreSight Program Flow Trace Architecture Specification0xFB0 Lock Access WO CoreSight Program Flow Trace Architecture Specification0xFB4 Lock Status RO CoreSight Program Flow Trace Architecture SpecificationARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 12-12ID062913Non-Confidential