ARM Cortex-A15 MPCore Processor Technical Reference Manual

Program Trace Macrocell12.7 Register descriptionsThis section describes the implementation-specific PTM registers in the Cortex-A15 MPCoreprocessor. Table 12-4 on page 12-11 provides cross references to individual registers.The ARM ® CoreSight Program Flow Trace Architecture Specification describes the other PTMregisters.12.7.1 Main Control RegisterThe ETMCR characteristics are:PurposeControls general operation of the PTM, such as whether tracing is enabledor is cycle-accurate.Usage constraints There are no usage constraints.ConfigurationsAvailable in all PTM configurations.Attributes See the register summary in Table 12-4 on page 12-11.Figure 12-2 shows the ETMCR bit assignments.31 30 29 28 27 25 24 23 16 15 14 13 12 11 10 9 8 7 61 0ReservedReservedReservedVMID traceenableReturn stackenableTimestampenableProcessorselectInstrumentationresource controlPowerdownStall processorBranchBroadcastDebug request controlProgBitReservedCycleAccurateReservedContextIDsizeFigure 12-2 ETMCR bit assignmentsTable 12-5 shows the ETMCR bit assignments.Table 12-5 ETMCR bit assignmentsBits Name Function[31] - SBZP.[30] VMID trace enable This bit controls VMID tracing. Set this bit to 1 to enable VMID tracing. Thereset value is 0.[29] Return stack enable Set this bit to 1 to enable use of the return stack. The reset value is 0.[28] Timestamp enable Set this bit to 1 to enable timestamping. The reset value is 0.[27:25] Processor select RAZ. This bit is not implemented.[24] Instrumentation resources access control RAZ. This bit is not implemented.[23:16] - SBZP.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 12-14ID062913Non-Confidential