ARM Cortex-A15 MPCore Processor Technical Reference Manual

RevisionsTable B-5 Differences between issue D and issue E (continued)Change Location AffectsUpdated the sequence for powering down the processor and theNEON and VFP power domainsAdded the processor powerdown mode as one of the powersequences that ARM recommendsAdding the deassertion of ACINACTM or AINACTS asconditions for exiting L2 WFI low-power stateProcessor power domain on page 2-30Processor powerdown mode on page 2-36L2 Wait for Interrupt on page 2-23r3p0r3p0All revisionsUpdated the reset value of the Main ID Register • Table 4-2 on page 4-4• Table 4-16 on page 4-14r3p0Updated bits[23:20] of the Main ID Register Main ID Register on page 4-27 r3p0Added Auxiliary Control Register 2 • Table 4-1 on page 4-13• Table 4-28 on page 4-25• Auxiliary Control Register 2 onpage 4-105r3p0Modified the L2 Auxiliary Control Register L2 Auxiliary Control Register on page 4-100 r3p0Removed the footnote and updated the value for Peripheral ID2RegisterUpdated the Performance Monitor Common Event Register 0 bitassignment table to indicate which event is implemented• Table 10-24 on page 10-32• Table 11-5 on page 11-12• Table 12-22 on page 12-30Table 11-4 on page 11-11All revisionsAll revisionsCorrected the reset value for bit[10] of the ETMCR Table 12-5 on page 12-14 All revisionsUpdated bit[0] of the ETMCR Table 12-5 on page 12-14 All revisionsUpdated bits[3:0] of the ETMIDR Table 12-10 on page 12-20 All revisionsUpdated the clock and clock enable signals table Table A-1 on page A-3 r3p0Updated the write address channel signals table Table A-10 on page A-14 r3p0Updated the power management signals table Table A-7 on page A-10 r3p0Table B-6 Differences between issue E and issue FChange Location AffectsUpdated the reset value of the Main ID Register • Table 4-2 on page 4-4• Table 4-16 on page 4-14r3p1Updated bits[23:20] of the Main ID Register Main ID Register on page 4-27 r3p1Updated information about external errors associated with a loadinstruction and with cache maintenance operations.Asynchronous errors on page 7-11All revisionsARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. B-4ID062913Non-Confidential