ARM Cortex-A15 MPCore Processor Technical Reference Manual

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Signal DescriptionsA.9 AXI interfacesFor descriptions of AXI interface signals, see the AMBA AXI Protocol Specification. In thissection, the suffix M in the signal name signifies an AXI master interface signal and the suffixS signifies an AXI slave interface signal.This section describes the AXI interfaces in:• AXI master interface signals.• ACP signals on page A-17.A.9.1AXI master interface signalsThe following sections describe the AXI master interface signals:• Clock and configuration signals.• Asynchronous error signals on page A-13.• Write address channel signals on page A-14.• Write data channel signals on page A-14.• Write response channel signals on page A-15.• Read address channel signals on page A-15.• Read data channel signals on page A-15.• Snoop address channel signals on page A-16.• Snoop data channel signals on page A-16.• Snoop response channel signals on page A-16.• Read/write acknowledge signals on page A-17.Clock and configuration signalsTable A-8 shows the clock and configuration signals for the AXI master interface.Signal Type DescriptionTable A-8 Clock and configuration signalsACLKENM Input AXI master bus clock enable. See Clocking and resets on page 2-8 for moreinformation.ACINACTM Input Snoop interface is inactive and no longer accepting requests.A64n128M Input Selects 64-bit or 128-bit AXI bus width:0 128-bit bus width.1 64-bit bus width.BROADCASTCACHEMAINT Input Enable broadcasting of cache maintenance operations to downstream caches:0 Cache maintenance operations are not broadcasted to downstreamcaches.1 Cache maintenance operations are broadcasted to downstream caches.This signal is only sampled during reset of the processor. See ACE configurations onpage 7-15 for more information.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. A-12ID062913Non-Confidential
Signal DescriptionsTable A-8 Clock and configuration signals (continued)Signal Type DescriptionBROADCASTINNER Input Enable broadcasting of inner shareable transactions:0 Inner shareable transactions are not broadcasted externally.1 Inner shareable transactions are broadcasted externally.If BROADCASTINNER is tied HIGH, you must also tie BROADCASTOUTERHIGH.This signal is only sampled during reset of the processor. See ACE configurations onpage 7-15 for more information.BROADCASTOUTER Input Enable broadcasting of outer shareable transactions:0 Outer shareable transactions are not broadcasted externally.1 Outer shareable transactions are broadcasted externally.This signal is only sampled during reset of the processor. See ACE configurations onpage 7-15 for more information.SYSBARDISABLE Input Disable broadcasting of barriers onto system bus:0 Barriers are broadcasted onto system bus, this requires an AMBA 4interconnect.1 Barriers are not broadcasted onto the system bus. This is compatiblewith an AXI3 interconnect.If SYSBARDISABLE is tied HIGH, you must tie the following signals LOW for fullAXI3 compatibility:• BROADCASTCACHEMAINT.• BROADCASTINNER.• BROADCASTOUTER.This signal is only sampled during reset of the processor. See ACE configurations onpage 7-15 for more information.Asynchronous error signalsTable A-9 shows the asynchronous error signals.Signal Type DescriptionTable A-9 Asynchronous error signalsnAXIERRIRQ Output Error indicator for AXI write transactions with a BRESP error condition. Writing 0 tobit[29] of the L2ECTLR clears the error indicator, see L2 Extended Control Register onpage 4-87 for more information.nINTERRIRQ Output Error indicator for:• L2 RAM double-bit ECC error.• Illegal writes to the GIC memory-map region, see GIC configuration on page 8-6.Writing 0 to bit[30] of the L2ECTLR clears the error indicator, see L2 Extended ControlRegister on page 4-87 for more information.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. A-13ID062913Non-Confidential
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®ARM®Cortex -A15 MPCoreProcessorR
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ContentsARM Cortex-A15 MPCore Proce
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Contents11.4 PMU register descripti
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PrefaceAbout this bookThis book is
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Preface(continued)Stylemonospace bo
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the Cortex-A1
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Introduction1.2.3 Debug architectur
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Introduction1.4 InterfacesThe proce
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Introduction• The L2 tag RAM regi
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IntroductionThe ARM product deliver
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Introduction1.7.5 r1p0 - r2p0The fo
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Introduction• Added L1 data TLB s
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Functional Description2.1 About the
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Functional DescriptionLoad/Store un
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Functional Description2.2 Interface
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Functional Description2.3 Clocking
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Functional DescriptionFigure 2-5 sh
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Functional DescriptionAll resets ar
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Functional DescriptionPowerup reset
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Functional Description• nPRESETDB
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Functional Description• L2 unifie
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Functional DescriptionOn entry into
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Functional DescriptionWhen the proc
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Functional DescriptionNoteFigure 2-
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Functional DescriptionRegional cloc
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Functional DescriptionTable 2-3 Val
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Functional Description4. Release th
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Functional DescriptionDebug power d
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Functional DescriptionNoteAfter a p
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Functional DescriptionThe external
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Programmers Model3.1 About the prog
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Programmers Model3.3 Advanced SIMD
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Programmers ModelYou can use the CP
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Programmers Model3.6 Large Physical
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Programmers Model3.8 Modes of opera
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Chapter 4System ControlThis chapter
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System Control4.2 Register summaryT
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System ControlOp1 CRm Op2 Name Rese
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System ControlTable 4-6 c5 register
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System ControlTable 4-8 c7 register
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System ControlTable 4-10 c9 registe
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System Control4.2.14 c15 registersT
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System ControlName CRn Op1 CRm Op2
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System Control4.2.19 Other system c
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System Control4.2.24 Performance mo
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System Control4.2.26 Virtualization
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System Control4.3 Register descript
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System ControlTo access the CTR, re
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System ControlTable 4-34 shows the
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System Control4.3.12 Memory Model F
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System ControlTable 4-40 ID_MMFR3 b
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System Control31 28 27 24 23 20 19
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System ControlTable 4-43 ID_ISAR2 b
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System ControlConfigurationsAvailab
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System ControlMCR p15, 4, , c0, c0,
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System ControlTable 4-52 SCTLR bit
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System Control31 30 29 28 27 26 25
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System ControlTable 4-53 ACTLR bit
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System ControlTable 4-53 ACTLR bit
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System ControlUsage constraints The
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System Control• The L2 internal a
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System Control31 30 29 28 27 26 25
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System ControlUsage constraints The
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System ControlTable 4-59 HCPTR bit
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System ControlTable 4-61 DFSR bit a
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System ControlTable 4-63 IFSR bit a
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System ControlConfigurationsAvailab
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System Control• UNKNOWN when exec
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System Control31 30 26 25 24 23 22
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System Control• Only accessible f
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System Control31 0DataFigure 4-40 I
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System ControlThe data returned fro
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System ControlThe data returned fro
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System Control31 24 23 21 20 19 18
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System Control4.3.60 L2 Auxiliary C
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System ControlTable 4-74 L2ACTLR bi
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System Control• Is only accessibl
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System ControlTable 4-79 L2MERRSR b
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Memory Management Unit5.1 About the
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Memory Management Unit5.3 TLB match
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Memory Management Unit• The TLB t
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Memory Management Unit5.6 Intermedi
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Memory Management Unit5.7 External
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Level 1 Memory System6.1 About the
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Level 1 Memory System6.3 L1 instruc
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Level 1 Memory System6.4 L1 data me
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Level 1 Memory SystemL1 or L2 cache
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Level 1 Memory SystemExternal globa
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Level 1 Memory System6.5 Program fl
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Level 1 Memory SystemReset:• Disa
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Chapter 7Level 2 Memory SystemThis
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Level 2 Memory System7.2 Cache orga
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Level 2 Memory System7.2.5 Register
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Level 2 Memory SystemNote• The L2
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Level 2 Memory System7.4 L2 cache p
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Level 2 Memory System7.6 Asynchrono
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Level 2 Memory SystemFor certain tr
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Level 2 Memory System7.7.6 Snoop fi
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Level 2 Memory SystemTable 7-6 show
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Chapter 8Generic Interrupt Controll
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Generic Interrupt Controller8.2 GIC
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Generic Interrupt Controller8.2.4 I
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Generic Interrupt Controller8.3 GIC
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Generic Interrupt ControllerOffset
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Generic Interrupt ControllerTable 8
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Generic Interrupt ControllerPrivate
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Generic Interrupt Controller0x1D043
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Generic Interrupt ControllerThe Cor
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Generic Interrupt ControllerTable 8
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Generic Interrupt Controller8.3.8 V
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Generic Timer9.1 About the Generic
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Generic Timer9.3 Generic Timer prog
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Chapter 10DebugThis chapter describ
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Debug• Operating systems.• Hard
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DebugnPRESETDBGThis signal initiali
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DebugTable 10-1 CP14 debug register
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DebugTable 10-1 CP14 debug register
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DebugTable 10-2 DBGDIDR bit assignm
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DebugTable 10-4 shows the DBGDRCR b
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DebugConfigurationsAttributesThe pr
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DebugTable 10-8 DBGBCR bit assignme
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DebugTable 10-10 shows the DBGWCR b
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Debug31 12 11 2 1 0ROMADDR[31:12]Re
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Debug10.4.12 OS Lock Status Registe
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DebugTable 10-15 shows the DBGPRCR
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DebugTable 10-16 DBGDSAR bit assign
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Debug31 1 0ReservedIntegration mode
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DebugTable 10-22 shows the DBGDEVID
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Debug10.4.23 Component Identificati
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Debug10.6 External debug interfaceT
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DebugIf software running on the pro
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Performance Monitor Unit11.1 About
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Performance Monitor Unit11.3 PMU re
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Performance Monitor UnitTable 11-1
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Performance Monitor Unit11.5 Effect
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Performance Monitor Unit11.7 Interr
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Chapter 12Program Trace MacrocellTh
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Program Trace Macrocell12.2 PTM opt
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Program Trace MacrocellYou can also
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Program Trace Macrocell12.5 PTM pro
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Program Trace Macrocellarchitecture
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Page 330 and 331: Program Trace Macrocell12.7.8 Confi
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Page 342 and 343: Cross Trigger13.1 About the cross t
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Page 346 and 347: Chapter 14NEON and VFP UnitThis cha
Page 348 and 349: NEON and VFP UnitARM DDI 0438I Copy
Page 350 and 351: NEON and VFP UnitSee the ARM ® Arc
Page 352 and 353: NEON and VFP UnitConfigurationsAvai
Page 354 and 355: NEON and VFP UnitTable 14-5 FPSCR b
Page 356 and 357: NEON and VFP UnitTable 14-6 MVFR1 b
Page 358 and 359: NEON and VFP Unit31 30 29 0Reserved
Page 360 and 361: Signal DescriptionsA.1 About the si
Page 362 and 363: Signal DescriptionsA.3 Reset signal
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Page 366 and 367: Signal DescriptionsA.6 Generic Time
Page 368 and 369: Signal DescriptionsA.8 Power manage
Page 372 and 373: Signal DescriptionsWrite address ch
Page 374 and 375: Signal DescriptionsTable A-14 Read
Page 376 and 377: Signal DescriptionsTable A-20 Write
Page 378 and 379: Signal DescriptionsA.10 External de
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Page 382 and 383: Signal DescriptionsA.12 Cross trigg
Page 384 and 385: Signal DescriptionsA.14 DFT and MBI
Page 386 and 387: Appendix BRevisionsThis appendix de
Page 388 and 389: RevisionsTable B-3 Differences betw
Page 390 and 391: RevisionsTable B-7 Differences betw
Page 392: RevisionsTable B-8 Differences betw
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ARM Cortex-A15 MPCore Processor Technical Reference Manual

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