ARM Cortex-A15 MPCore Processor Technical Reference Manual

NEON and VFP UnitMedia and VFP Feature Register 1The MVFR1 characteristics are:PurposeTogether with MVFR0, describes the features provided by the AdvancedSIMD and VFP extensions.Usage constraints Only accessible from PL1 or higher.ConfigurationsAvailable if VFP is implemented. The MVFR1 register is a Configurableaccess register which is a system control register that secure software canconfigure the access to. When the settings in the CPACR, see CoprocessorAccess Control Register on page 4-62, permit access to the MVFR1register:• It is accessible in Non-secure state only if the NSACR.{CP11,CP10} bits are both set to 1. See Non-Secure Access ControlRegister on page 4-65.• Bits in the HCPTR, see Hyp Coprocessor Trap Register onpage 4-71, also control Non-secure access to the register.Attributes See the register summary in Table 14-3 on page 14-6.Figure 14-3 shows the MVFR1 bit assignments.31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0A_SIMDFMACVFPHPFPA_SIMDHPFPA_SIMDSPFPA_SIMDintegerA_SIMDload/storeD_NaNmodeFtZmodeFigure 14-3 MVFR1 bit assignmentsTable 14-6 shows the MVFR1 bit assignments.Table 14-6 MVFR1 bit assignmentsBits Name Function[31:28] A_SIMD FMAC Indicates whether the Advanced SIMD or VFP supports fused multiply accumulate operations:0x1 Supported.[27:24] VFP HPFP Indicates whether the VFP supports half-precision floating-point conversion operations:0x1 Supported.[23:20] A_SIMD HPFP Indicates whether the Advanced SIMD extension supports half-precision floating-pointconversion operations:0x1 Supported.If Advanced SIMD is implemented, the reset value is 0x1.If Advanced SIMD is not implemented, the reset value is 0x0.[19:16] A_SIMD SPFP Indicates whether the Advanced SIMD extension supports single-precision floating-pointoperations:0x1 Supported.If Advanced SIMD is implemented, the reset value is 0x1.If Advanced SIMD is not implemented, the reset value is 0x0.[15:12] A_SIMD integer Indicates whether the Advanced SIMD extension supports integer operations:0x1 Supported.If Advanced SIMD is implemented, the reset value is 0x1.If Advanced SIMD is not implemented, the reset value is 0x0.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 14-10ID062913Non-Confidential