ARM Cortex-A15 MPCore Processor Technical Reference Manual

Generic Timer9.2 Generic Timer functional descriptionThe Cortex-A15 MPCore Generic Timer includes:• A physical counter that contains the count value of the system counter.• A virtual counter that indicates virtual time. The virtual counter contains the value of thephysical counter minus a 64-bit virtual offset.• A set of four timers, one for each processor in the MPCore device.The four timers are of the following:• A PL1 physical timer. The registers for the PL1 physical timer are banked to provideSecure and Non-secure copies.• A PL2 physical timer.• A virtual timer.The Cortex-A15 MPCore processor does not include the system counter which resides in theSoC. The system counter value is distributed to the Cortex-A15 MPCore processor with asynchronous binary encoded 64-bit bus, CNTVALUEB[63:0].Each timer provides an active-LOW interrupt output that is an external pin to the SoC and issent to the GIC as a Private Peripheral Interrupt (PPI). See Interrupt sources on page 8-4 forthe ID and PPI allocation of the Timer interrupts.Table 9-1 shows the signals that are the external interrupt output pins.Table 9-1 Generic Timer signalsSignal anCNTNSIRQ[n:0]nCNTSIRQ[n:0]nCNTHPIRQ[n:0]nCNTVIRQ[n:0]DescriptionNon-secure PL1 physical timer eventSecure PL1 physical timer eventNon-secure PL2 physical timer eventVirtual timer eventa. n is the number of processors present in the MPCoredevice, minus one.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 9-3ID062913Non-Confidential