ARM Cortex-A15 MPCore Processor Technical Reference Manual

DebugTable 10-23 DBGDEVID bit assignments (continued)Bits Name Function[15:12] VectorCatch Defines the form of the vector catch event implemented:b0000 The processor implements address matching form of vector catch.[11:8] BPAddrMask Indicates the level of support for the Immediate Virtual Address (IVA) matching breakpointmasking capability:b1111 Breakpoint address masking not implemented. DBGBCRn[28:24] areUNK/SBZP.[7:4] WPAddrMask Indicates the level of support for the DVA matching watchpoint masking capability:b0001 Watchpoint address mask implemented.[3:0] PCsample Indicates the level of support for Program Counter sampling using debug registers 40, 41 and 42:b0011 DBGPCSR, DBGCIDSR and DBGVIDSR are implemented as debug registers40, 41, and 42.10.4.22 Peripheral Identification RegistersThe Peripheral Identification Registers provide standard information required for allcomponents that conform to the ARM Debug Interface v5 specification. They are a set of eightregisters, listed in register number order in Table 10-24.Table 10-24 Summary of the Peripheral Identification RegistersRegister Value OffsetPeripheral ID4 0x04 0xFD0Peripheral ID5 0x00 0xFD4Peripheral ID6 0x00 0xFD8Peripheral ID7 0x00 0xFDCPeripheral ID0 0x0F 0xFE0Peripheral ID1 0xBC 0xFE4Peripheral ID2 0x3B 0xFE8Peripheral ID3 0x00 0xFECOnly bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, theeight Peripheral ID Registers define a single 64-bit Peripheral ID.The ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition describes theseregisters.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 10-32ID062913Non-Confidential