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ARM Cortex-A15 MPCore Processor Technical Reference Manual

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Generic Interrupt Controller0x1D0431 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0GICD_SPISR[0] for IRQS[31:0]31 2 1 00x1D08GICD_SPISR[1] for IRQS[63:32]63 34 33 320x1D0CGICD_SPISR[2] for IRQS[95:64].95.66 65 64..0x1D1CGICD_SPISR[6] for IRQS[223:192]223192Figure 8-5 GICD_SPISR address mapThe Distributor provides up to seven registers to support 224 SPIs. If the GIC is configured touse fewer than 224 SPIs, it reduces the number of registers accordingly. For locations whereinterrupts are not implemented, the bit is RAZ/WI.8.3.3 CPU interface register summaryEach CPU interface block provides the interface for a <strong>Cortex</strong>-<strong>A15</strong> <strong>MPCore</strong> processor thatoperates with the GIC. Each CPU interface provides a programming interface for:• Enabling the signaling of interrupt requests by the CPU interface.• Acknowledging an interrupt.• Indicating completion of the processing of an interrupt.• Setting an interrupt priority mask for the processor.• Defining the preemption policy for the processor.• Determining the highest priority pending interrupt for the processor.For more information on CPU interfaces, see the <strong>ARM</strong> Generic Interrupt ControllerArchitecture Specification.Table 8-9 shows the register map for the CPU interface. The offsets in this table are relative tothe CPU interface block base address as shown in Table 8-1 on page 8-4.All the registers in Table 8-9 are word-accessible. Registers not described in this table areRAZ/WI.Offset Name Type Reset DescriptionTable 8-9 CPU interface register summary0x0000 GICC_CTLR RW 0x00000000 CPU Interface Control Register, see <strong>ARM</strong> Generic Interrupt ControllerArchitecture Specification0x0004 GICC_PMR RW 0x00000000 Interrupt Priority Mask Register, see <strong>ARM</strong> Generic Interrupt ControllerArchitecture Specification0x0008 GICC_BPR RW 0x00000002 (S) a0x00000003 (NS) bBinary Point Register, see <strong>ARM</strong> Generic Interrupt ControllerArchitecture Specification<strong>ARM</strong> DDI 0438I Copyright © 2011-2013 <strong>ARM</strong>. All rights reserved. 8-15ID062913Non-Confidential

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