ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 1 Memory System6.3.3 Fill buffersThe instruction cache is fed by dual fill buffers that hold instructions returned from the L2 cacheon a linefill operation, or instructions from non-cacheable regions. The fill buffers arenon-blocking. An instruction cache hit can bypass an in-progress cache miss, even before thecritical word is returned.6.3.4 Non-cacheable fetchingFetches that occur when the instruction cache is disabled, or from a page with attributes notindicating inner cacheable, do not result in the line entering the instruction cache. Incominginstructions from the L2 cache are stored in the fill buffers until the fetch reaches the end of thecache line or a non-sequential fetch occurs, whichever occurs first. Therefore, multiple repeatedfetches from the same address can occur in sequence when a region is not given cacheableattributes.6.3.5 Parity error handlingThe instruction cache implements one parity bit per 16-bits of instruction data. The instructioncache tag array is also protected by one parity bit per tag entry. Parity errors invalidate theoffending cache line, and force a refetch from the L2 cache on the next access. No aborts aregenerated on parity errors that occur within the instruction cache. The location of a parity erroris reported in the CPU Memory Error Syndrome Register, see CPU Memory Error SyndromeRegister on page 4-107. Because the data cache shares this register, there is no guarantee thatthis register contains the location of the last instruction side parity error.6.3.6 Cache line length and heterogeneous systemsSystems that are comprised of both the Cortex-A15 MPCore processor and other processorsoperating under a shareable memory system must consider differences in the cache line length.The Cortex-A15 MPCore processor L1 caches contain 64-byte lines. Other processors,however, can feature caches that support cache line lengths different than those of theCortex-A15 MPCore processor. System software often requires invalidation of a range ofaddresses that might be present in multiple processors. This is accomplished with a loop ofinvalidate cache by MVA CP15 operations that step through the address space in cacheline-sized strides. For code to be portable across all ARMv7-A architecture-compliant devices,system software queries the CP15 Cache Type Register to obtain the stride size, see Cache TypeRegister on page 4-28 for more information.Systems that contain a combination of processors with 64-byte and 32-byte lines must handledata cache side operations within the interconnect, but it is not a requirement that theinterconnect handles instruction side operations. The Cortex-A15 MPCore processor containsthe IMINLN signal, that on reset, sets the value of the IminLine field within the Cache TypeRegister. You must set this signal 0 or 1, depending on the minimum instruction cache line sizein the system. When IMINLN is set to 0, the minimum system-wide instruction cache line sizeis 32 bytes. When IMINLN is set to 1, the minimum system-wide instruction cache line size is64 bytes. This signal is only sampled at reset.Note• This signal does not affect internal instruction cache line size or operation of the cachemaintenance commands.• A system containing only Cortex-A15 MPCore processors must set the IMINLN signalto 1 on all processors in the system.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 6-5ID062913Non-Confidential