ARM Cortex-A15 MPCore Processor Technical Reference Manual

Introduction1.6 Product documentation and design flowThis section describes the Cortex-A15 MPCore processor books and how they relate to thedesign flow in:• Documentation.• Design flow on page 1-10.See Additional reading on page ix for more information about the books described in thissection. For information on the relevant architectural standards and protocols, see Complianceon page 1-3.1.6.1 DocumentationThe Cortex-A15 MPCore processor documentation is as follows:Technical Reference ManualThe Technical Reference Manual (TRM) describes the functionality and theeffects of functional options on the behavior of the Cortex-A15 MPCoreprocessor. It is required at all stages of the design flow. The choices made in thedesign flow can mean that some behavior described in the TRM is not relevant.If you are programming the Cortex-A15 MPCore processor, additionalinformation must be obtained from:• the implementer to determine the build configuration of the implementation• the integrator to determine the pin configuration of the device that you areusing.Note• The out-of-order design of the Cortex-A15 MPCore processor pipelinemakes it impossible to provide accurate timing information for complexinstructions. The timing of an instruction can be affected by factors such as:— Other concurrent instructions.— Memory system activity.— Events outside the instruction flow.• Timing information has been provided in the past for some ARMprocessors to assist in detailed hand tuning of performance critical codesequences or in the development of an instruction scheduler within acompiler. This timing information is not required for producing optimizedinstruction sequences on the Cortex-A15 MPCore processor. Theout-of-order pipeline of the Cortex-A15 MPCore processor can scheduleand execute the instructions in an optimal fashion without any instructionreordering required.Configuration and Sign-off GuideThe ARM Configuration and Sign-off Guide (CSG) describes:• The available build configuration options and related issues in selectingthem.• How to configure the Register Transfer Level (RTL) source files with thebuild configuration options.• How to integrate RAM arrays.• How to run test vectors.• The processes to sign off the configured design.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 1-9ID062913Non-Confidential