ARM Cortex-A15 MPCore Processor Technical Reference Manual

NEON and VFP UnitConfigurationsAvailable if VFP is implemented. The FPSCR register is a Configurableaccess register which is a system control register that secure software canconfigure the access to. When the settings in the CPACR, see CoprocessorAccess Control Register on page 4-62, permit access to the FPSCRregister:• It is accessible in Non-secure state only if the NSACR.{CP11,CP10} bits are both set to 1. See Non-Secure Access ControlRegister on page 4-65.• Bits in the HCPTR, see Hyp Coprocessor Trap Register onpage 4-71, also control Non-secure access to the register.Attributes See the register summary in Table 14-3 on page 14-6.Figure 14-2 shows the FPSCR bit assignments.31 30 29 28 27 26 25 24 23 22 21 20 19 18 16 15 8 7 6 5 4 3 2 1 0NZ C V Len ReservedQCAHPDNFZRModeStrideReservedIDCReservedIXCUFCOFCDZCIOCFigure 14-2 FPSCR bit assignmentsTable 14-5 shows the FPSCR bit assignments.Table 14-5 FPSCR bit assignmentsBits Field Function[31] N VFP Negative condition code flag.Set to 1 if a VFP comparison operation produces a less than result.[30] Z VFP Zero condition code flag.Set to 1 if a VFP comparison operation produces an equal result.[29] C VFP Carry condition code flag.Set to 1 if a VFP comparison operation produces an equal, greater than, or unordered result.[28] V VFP Overflow condition code flag.Set to 1 if a VFP comparison operation produces an unordered result.[27] QC Cumulative saturation bit.This bit is set to 1 to indicate that an Advanced SIMD integer operation has saturated after 0 waslast written to this bit.If Advanced SIMD is not implemented, this bit is UNK/SBZP.[26] AHP Alternative Half-Precision control bit:0 IEEE half-precision format selected.1 Alternative half-precision format selected.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 14-8ID062913Non-Confidential