ARM Cortex-A15 MPCore Processor Technical Reference Manual

Introduction1.5 Implementation optionsTable 1-1 lists the implementation options for the Cortex-A15 MPCore processor.Table 1-1 Cortex-A15 MPCore processor implementation optionsFeatureNumber of processorsL2 cache sizeRange of optionsUp to four processorsL2 cache size of:• 512KB.• 1MB.• 2MB.• 4MB.L2 tag RAM register slice 0 or 1L2 data RAM register slice 0, 1 or 2L2 arbitration register sliceL2 logic idle gated clockRegional gated clocks aECC/parity supportNEONVFPGeneric Interrupt ControllerIncluded or NotIncluded or NotIncluded or NotSupported in L1 and L2, L2 only, or noneIncluded or NotIncluded or NotIncluded or NotShared Peripheral Interrupts 0 to 224, in steps of 32Processor clock stop pins aPower switch and clamp pinsL1 data TLB page table sizeIncluded or NotIncluded or NotL1 data TLB page table size of:• 4KB entries only.• 4KB or 1MB entries.a. This feature is not available in revisions prior to r3p0.Note• All the processors share an integrated L2 cache and GIC. Each processor has the sameconfiguration for NEON, VFP, and L1 ECC or parity.• If you configure the design for one processor, it retains the system level coherency supportand the ACP slave port.• If you configure the design to exclude VFP, NEON is not available. You cannot configurethe design to exclude VFP but include NEON.• If you configure the design to exclude the GIC, SPIs and the remaining GIC signals arenot available, except PERIPHBASE[39:15].ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 1-7ID062913Non-Confidential