ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-74 L2ACTLR bit assignments (continued)Bits Name Function[8] Disable DVM/CMO messagebroadcastDisables Distributed Virtual Memory (DVM) transactions and cache maintenanceoperation message broadcast:0 Enables DVM and cache maintenance operation message broadcast.This is the reset value.1 Disables DVM and cache maintenance operation message broadcast.[7] Enable hazard detect timeout Enables hazard detect timeout:0 Disables hazard detect timeout. This is the reset value.1 Enables hazard detect timeout.[6] Disable shareable transactionsfrom masterDisables shareable transactions from master:0 Enables shareable transactions from master. This is the reset value.1 Disables shareable transactions from master.[5] - Reserved, RAZ/WI.[4] Disable WriteUnique andWriteLineUnique transactionsfrom master[3] Disable clean/evict push toexternal[2] Limit to one request per tagbank[1] Enable arbitration replaythreshold timeoutDisables WriteUnique and WriteLineUnique transactions from master:0 Enables WriteUnique and WriteLineUnique transactions from master.This is the reset value.1 Disables WriteUnique and WriteLineUnique transactions from master.Disables clean/evict push to external:0 Enables clean/evict to be pushed out to external. This is the reset value.1 Disables clean/evict from being pushed to external.Limit to one request per tag bank:0 Normal behavior of permitting parallel requests to the tag banks. This isthe reset value.1 Limits to one request per tag bank.Enable arbitration replay threshold timeout:0 Disables arbitration replay threshold timeout. This is the reset value.1 Enables arbitration replay threshold timeout.[0] Disable prefetch forwarding Disables prefetch forwarding:0 Enables prefetch forwarding. This is the reset value.1 Disables prefetch forwarding.a. This bit is not available in revisions prior to r3p0.To access the L2ACTLR, read or write the CP15 register with:MRC p15, 1, , c15, c0, 0; Read L2 Auxiliary Control RegisterMCR p15, 1, , c15, c0, 0; Write L2 Auxiliary Control Register4.3.61 L2 Prefetch Control RegisterThe L2PFR characteristics are:PurposeProvides control options for the L2 automatic hardware prefetcher.Usage constraints The L2PFR:• Is a read/write register.• Is Common to the Secure and Non-secure states.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-103ID062913Non-Confidential