ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control4.2 Register summaryThis section gives a summary of the CP15 system control registers. For more information onusing the CP15 system control registers, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition.The system control coprocessor is a set of registers that you can write to and read from. Someof the registers permit more than one type of operation.The following subsections describe the CP15 system control registers grouped by CRn order,and accessed by the MCR and MRC instructions in the order of CRn, Op1, CRm, Op2:• c0 registers on page 4-4.• c1 registers on page 4-5.• c2 registers on page 4-6.• c3 registers on page 4-6.• c5 registers on page 4-6.• c6 registers on page 4-7.• c7 registers on page 4-7.• c8 registers on page 4-9.• c9 registers on page 4-10.• c10 registers on page 4-11.• c12 registers on page 4-12.• c13 registers on page 4-12.• c14 registers on page 4-12.• c15 registers on page 4-13.The Cortex-A15 MPCore processor supports the Virtualization Extensions (VE), the LargePhysical Address Extension (LPAE), and the Generic Timer. See Virtualization Extensionsarchitecture on page 3-7, Large Physical Address Extension architecture on page 3-8, andChapter 9 Generic Timer for more information. The VE, LPAE, and Generic Timer contain anumber of 64-bit registers. The following subsection describes these registers and providescross references to individual register descriptions:• 64-bit registers on page 4-13.In addition to listing the CP15 system control registers by CRn ordering, the followingsubsections describe the CP15 system control registers by functional group:• Identification registers on page 4-14.• Virtual memory control registers on page 4-15.• PL1 Fault handling registers on page 4-16.• Other system control registers on page 4-17.• Cache maintenance operations on page 4-17.• TLB maintenance operations on page 4-18.• Address translation operations on page 4-19.• Miscellaneous operations on page 4-20.• Performance monitor registers on page 4-21.• Security Extensions registers on page 4-22.• Virtualization Extensions registers on page 4-23.• Hyp mode TLB maintenance operations on page 4-24.• Generic Timer registers on page 4-25.• Implementation defined registers on page 4-25.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-3ID062913Non-Confidential