ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-52 SCTLR bit assignments (continued)Bits Name Access Function[20] UWXN Banked Unprivileged write permission implies PL1 Execute Never (XN). This bit can be used to requireall memory regions with unprivileged write permissions to be treated as XN for accesses fromsoftware executing at PL1:0 Regions with unprivileged write permission are not forced to be XN. This is thereset value.1 Regions with unprivileged write permission are forced to be XN for accesses fromsoftware executing at PL1.This bit resets to 0 in both the Secure and the Non-secure copy of the register. See the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition for more information.[19] WXN Banked Write permission implies Execute Never (XN). This bit can be used to require all memory regionswith write permissions to be treated as XN:0 Regions with write permission are not forced to be XN. This is the reset value.1 Regions with write permissions are forced to be XN.This bit resets to 0 in both the Secure and the Non-secure copy of the register. See the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition for more information.[18] - - Reserved, RAO/SBOP.[17] - - Reserved, RAZ/WI.[16] - - Reserved, RAO/SBOP.[15] - - Reserved, RAZ/SBZP.[14] - - Reserved, RAZ/WI.[13] V Banked Vectors bit. This bit selects the base address of the exception vectors:0 Normal exception vectors, base address 0x00000000. This base address can beremapped by updating the Vector Base Address Register. See the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition.1 High exception vectors, base address 0xFFFF0000. This base address is neverremapped.The primary input VINITHI defines the reset value of the V bit.[12] I Banked Instruction cache enable. This is a global enable bit for instruction caches:0 Instruction caches disabled. This is the reset value.1 Instruction caches enabled.[11] Z Banked Branch prediction enable. This bit is used to enable branch prediction, also called program flowprediction:0 Program flow prediction disabled. This is the reset value.1 Program flow prediction enabled.[10] SW Banked SWP/SWPB enable bit. This bit enables the use of SWP and SWPB instructions:0 SWP and SWPB are UNDEFINED. This is the reset value.1 SWP and SWPB perform as described in the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition.[9:7] - - Reserved, RAZ/SBZP.[6:3] - - Reserved, RAO/SBOP.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-56ID062913Non-Confidential