ARM Cortex-A15 MPCore Processor Technical Reference Manual

Generic Interrupt ControllerThe GICD_IPRIORITYRn, GICD_ITARGETSRn, GICD_CPENDSGIR andGICD_SPENDSGIR registers are byte-accessible and word-accessible. All other registers inTable 8-3 are word-accessible. Registers not described in Table 8-3 are RAZ/WI.Offset Name Type Reset DescriptionTable 8-3 Distributor register summary0x000 GICD_CTLR RW a 0x00000000 Distributor Control Register, see ARM GenericInterrupt Controller Architecture Specification0x004 GICD_TYPER RO Configuration dependent Interrupt Controller Type Register on page 8-100x008 GICD_IIDR RO 0x0000043B Distributor Implementer Identification Registeron page 8-110x080 - 0x09C GICD_IGROUPRn RW b 0x00000000 Interrupt Group Registers, see ARM GenericInterrupt Controller Architecture Specification0x1000x104 - 0x11CGICD_ISENABLERnRW0x0000FFFF c0x00000000Interrupt Set-Enable Registers, see ARM GenericInterrupt Controller Architecture Specification0x1800x184 - 0x19CGICD_ICENABLERnRW0x0000FFFF c0x00000000Interrupt Clear-Enable Registers, see ARMGeneric Interrupt Controller ArchitectureSpecification0x200 - 0x21C GICD_ISPENDRn RW 0x00000000 Interrupt Set-Pending Registers, see ARM GenericInterrupt Controller Architecture Specification0x280 - 0x29C GICD_ICPENDRn RW 0x00000000 Interrupt Clear-Pending Registers, see ARMGeneric Interrupt Controller ArchitectureSpecification0x300 - 0x31C GICD_ISACTIVERn RW 0x00000000 Interrupt Set-Active Registers, see ARM GenericInterrupt Controller Architecture Specification0x380 - 0x39C GICD_ICACTIVERn RW 0x00000000 Interrupt Clear-Active Registers, see ARMGeneric Interrupt Controller ArchitectureSpecification0x400 - 0x4FC GICD_IPRIORITYRn RW d 0x00000000 Interrupt Priority Registers, see ARM GenericInterrupt Controller Architecture Specification0x800 - 0x81CGICD_ITARGETSRn e Generic Interrupt Controller ArchitectureRO Configuration dependent Interrupt Processor Targets Registers, see ARMSpecification0x820 - 0x8FC RW f 0x000000000xC00RO 0xAAAAAAAA g0xC04 GICD_ICFGRn RO 0x55540000 gInterrupt Configuration Register on page 8-120xC08 - 0xC3C RW 0x55555555 g0xD00 GICD_PPISR RO 0x00000000 Private Peripheral Interrupt Status Register onpage 8-130xD04 -0xD1C GICD_SPISRn RO 0x00000000 Shared Peripheral Interrupt Status Registers onpage 8-130xF00 GICD_SGIR h WO - Software Generated Interrupt Register, see ARMGeneric Interrupt Controller ArchitectureSpecificationARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 8-8ID062913Non-Confidential