ARM Cortex-A15 MPCore Processor Technical Reference Manual

Functional DescriptionWhen the processor exits from WFI low-power state, STANDBYWFI for that processor isdeasserted. When the L2 memory system logic exits from WFI low-power state,STANDBYWFIL2 is deasserted.Figure 2-13 shows the L2 WFI timing for a 4-processor configuration.CLKSTANDBYWFI[3:0]ACINACTMAINACTSSTANDBYWFIL2CLKENInternal L2 clocknIRQFigure 2-13 L2 Wait For Interrupt timingProcessor retention in WFI and WFE low-power stateNoteThe processor retention in WFI and WFE low-power state is not available in revisions prior tor3p0.When a processor is in WFI or WFE low-power state, the clocks to that processor are stopped.The clocks might start for short periods of time during the WFI or WFE low-power state to allowthe processor to handle snoops or other short events without leaving WFI or WFE low-powerstate.Whenever the clocks to a processor are stopped, it is possible for an external power controllerto lower the voltage of that processor to a lower level where all state is retained while leakageis reduced. However, this is only possible if the external power controller can guarantee that theclocks do not restart without first allowing the voltage to be raised to the level required fornormal operation. The Cortex-A15 MPCore processor has an interface that allows an externalpower controller to place one or more processors into a retention state. The external powercontroller ensures that the clocks do not restart without first allowing the power controller toexit the retention state.When the clocks are stopped because the processor is in WFI or WFE low-power state, theQACTIVE signal is deasserted LOW for that processor as Figure 2-14 on page 2-25 shows.This indicates that retention is possible for that processor. The external power controller canplace that processor in retention state by asserting QREQn LOW. The Cortex-A15 MPCoreprocessor accepts the retention request by asserting QACCEPTn LOW. While QREQn andQACCEPTn are both asserted LOW, the processor is in quiescent state and the clocks to thatprocessor remain stopped as long as QREQn remains asserted LOW. The external powercontroller can safely lower the voltage of that processor to a retention level.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 2-24ID062913Non-Confidential