ARM Cortex-A15 MPCore Processor Technical Reference Manual

Functional DescriptionRegional clock gatingNoteThis feature is not available in revisions prior to r3p0.In addition to extensive local clock gating to register flops, you can configure the Cortex-A15MPCore processor to include regional clock gates that can perform additional clock gating oflogic blocks such as the register banks. This can potentially reduce dynamic power dissipation.You can set bit[31] of the ACTLR2 to 1 to enable regional clock gating for each processor. SeeAuxiliary Control Register 2 on page 4-105.You can set bit[26] of the L2ACTLR to 1 to enable regional clock gating in the L2, InterruptController, and Timer. See L2 Auxiliary Control Register on page 4-100.At reset, both of these bits are clear and the regional clock gates enables are tied HIGH. Youmust set these bits to 1 to enable additional clock gating in the regional clock gates forpotentially reduced dynamic power dissipation.2.4.2 Power domainsThe processor can support multiple power domains. Each processor supports the followingpower domains:• The processor, including the Debug, PTM, and all of the L1 cache and branch predictionRAMs but excluding the NEON and VFP logic.• The NEON and VFP logic.For the remaining logic, the following power domains are supported:• The L2 cache tag bank RAMs.• The L2 control, the GIC and the Generic Timer logic.• The Debug APB interface, CTI, and CTM logic.NoteThe design does not support a separate power domain for the L1 cache and branch predictionRAMs within the processor. It does not support L1 cache retention when the processor ispowered down.Figure 2-16 on page 2-29 shows the supported power domains and placeholders where you caninsert clamps for a single processor in the multiprocessor.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 2-28ID062913Non-Confidential