ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-41 shows the ID_ISAR0 bit assignments.Table 4-41 ID_ISAR0 bit assignmentsBits Name Function[31:28] - Reserved, RAZ.[27:24] Divide_instrs Indicates support for Divide instructions.0x2 Processor supports:• SDIV and UDIV in the Thumb instruction set.• SDIV and UDIV in the ARM instruction set.[23:20] Debug_instrs Indicates the supported Debug instructions:0x1 Processor supports BKPT instruction.[19:16] Coproc_instrs Indicates the supported Coprocessor instructions:0x0 None supported, except for separately attributed architectures including CP15,CP14, and Advanced SIMD and VFP.[15:12] CmpBranch_instrs Indicates the supported combined Compare and Branch instructions in the Thumb instruction set:0x1 Processor supports CBNZ and CBZ instructions.[11:8] Bitfield_instrs Indicates the supported BifField instructions:0x1 Processor supports BFC, BFI, SBFX, and UBFX instructions.[7:4] BitCount_instrs Indicates the supported Bit Counting instructions:0x1 Processor supports CLZ instruction.[3:0] Swap_instrs Indicates the supported Swap instructions in the ARM instruction set:0x0 Not supported.To access the ID_ISAR0, read the CP15 register with:MRC p15, 0, , c0, c2, 0 ; Read Instruction Set Attribute Register 04.3.16 Instruction Set Attribute Register 1The ID_ISAR1 characteristics are:PurposeProvides information about the instruction set that the processor supports.Usage constraints The ID_ISAR1 is:• A read-only register.• Common to the Secure and Non-secure states.• Only accessible from PL1 or higher.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-2 on page 4-4.Figure 4-14 on page 4-42 shows the ID_ISAR1 bit assignments.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-41ID062913Non-Confidential