ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control• UNKNOWN when executing in Non-secure modes other than Hypmode.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-26 on page 4-23.Figure 4-37 shows the HSR bit assignments.31 26 25 24 0ECISSILFigure 4-37 HSR bit assignmentsTable 4-68 shows the HSR bit assignments.Table 4-68 HSR bit assignmentsBits Name Function[31:26] EC Exception class. The exception class for the exception that is taken to Hyp mode.When zero, this field indicates that the reason for the exception is not known. In thiscase, the other fields in this register are UNKNOWN. Otherwise, the field holds theexception class for the exception. See the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition for more information.[25] IL Instruction length. Indicates the size of the instruction that has been trapped to Hypmode:0 16-bit instruction.1 32-bit instruction.This field is not valid for:• Prefetch Aborts.• Data Aborts that do not have ISS information, or for which the ISS is not valid.In these cases the field is UNK/SBZP.[24:0] ISS Instruction specific syndrome. The interpretation of this field depends on the value ofthe EC field. See Encoding of ISS[24:20] when HSR[31:30] is 0b00.Encoding of ISS[24:20] when HSR[31:30] is 0b00For EC values that are nonzero and have the two most-significant bits 0b00, ISS[24:20]provides the condition field for the trapped instruction, together with a valid flag for this field.The encoding of this part of the ISS field is:CV, ISS[24] Condition valid. Possible values of this bit are:0 The COND field is not valid.1 The COND field is valid.When an instruction is trapped, CV is set to 1.COND, ISS[23:20]The Condition field for the trapped instruction. This field is valid only when CVis set to 1.If CV is set to 0, this field is UNK/SBZP.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-84ID062913Non-Confidential