ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control• Common to the Secure and Non-secure states.• Only accessible from PL1 or higher.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-2 on page 4-4.Figure 4-12 shows the ID_MMFR3 bit assignments.31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0ReservedSupersection supportCached memory sizeCoherent walkMaintenance broadcastBranch predictor maintenanceCache maintenance by set/wayCache maintenance by MVATable 4-40 shows the ID_MMFR3 bit assignments.Figure 4-12 ID_MMFR3 bit assignmentsTable 4-40 ID_MMFR3 bit assignmentsBits Name Function[31:28] Supersection support Indicates support for supersections:0x0Processor supports supersections.[27:24] Cached memory size Indicates the physical memory size supported by the processor caches:0x2Processor caches support 40-bit physical address range.[23:20] Coherent walk Indicates whether translation table updates require a clean to the point of unification:0x1Updates to the translation tables do not require a clean to the point ofunification to ensure visibility by subsequent translation table walks.[19:16] - Reserved, RAZ.[15:12] Maintenance broadcast Indicates whether cache, TLB and branch predictor operations are broadcast:0x2Cache, TLB and branch predictor operations affect structures accordingto shareability and defined behavior of instructions.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-39ID062913Non-Confidential