ARM Cortex-A15 MPCore Processor Technical Reference Manual

Functional DescriptionTo power down the Cortex-A15 MPCore processor, apply the following sequence:1. Ensure all non-lead processors are in shutdown mode, see Processor power domain onpage 2-30.2. For the remaining and lead processor, follow steps 1 and 2 in Processor power domain onpage 2-30.3. Ensure the ACP master does not send further requests to the individual processor. AssertAINACTS to idle the ACP slave interface after all responses are received.4. Ensure any system snooping to the Cortex-A15 MPCore processor is disabled.5. Disable L2 prefetches by writing 0x00000400 to the L2 Prefetch Control Register. See L2Prefetch Control Register on page 4-103.6. Execute an ISB instruction to ensure the L2 Prefetch Control Register write is complete.See L2 Prefetch Control Register on page 4-103.7. Execute a DSB instruction to ensure completion of any prior prefetch requests.8. Clean and invalidate all data from the L2 data cache.9. Assert ACINACTM to idle the AXI master interface after all responses are received.10. Ensure system interrupts to the Cortex-A15 MPCore processor are disabled.11. Set the DBGOSDLR.DLK, OS Double Lock control bit, that forces the debug interfacesto be quiescent.12. Follow steps 3 to 9 in Processor power domain on page 2-30.13. Wait until the STANDBYWFIL2 output is asserted to indicate that the L2 memorysystem is idle.14. Activate the output clamps of the Cortex-A15 MPCore processor in the SoC.15. Remove power from the L2 control and L2 RAM power domains.To power up the Cortex-A15 MPCore processor, apply the following sequence:1. For each processor in the multiprocessor, assert nCPUPORESET LOW.2. For the lead processor in the multiprocessor, assert nPRESETDBG and nL2RESETLOW, and hold L2RSTDISABLE LOW.3. Apply power to the processor, L2 control, L2 RAM and debug power domains whilekeeping the signals described in steps 1 and 2 LOW.4. Release the output clamps of the Cortex-A15 MPCore processor in the SoC.5. Continue a normal powerup reset sequence.2.4.4 Event communication using WFE and SEV instructionsIn the Cortex-A15 MPCore processor, an external agent can participate in the WFE and SEVevent communication using the EVENTI pin. When this pin is asserted, it sends an eventmessage to all the processors in the multiprocessor. This is similar to executing an SEVinstruction on one processor in the multiprocessor. This enables the external agent to signal tothe processor that it has released a semaphore and that the processor can leave the WFE standbypower saving mode. The EVENTI input pin must remain HIGH for at least one CLK cycle tobe visible by the processors.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 2-37ID062913Non-Confidential