ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlName CRn Op1 CRm Op2 Reset Width DescriptionTable 4-17 Virtual memory registers (continued)MAIR0 0 UNK 32-bit Memory Attribute Indirection Register 0, see theARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionNMRR 1 0x44E048E0 32-bit Normal Memory Remap Register, see the ARM ®Architecture Reference Manual ARMv7-A andARMv7-R editionMAIR1 1 UNK 32-bit Memory Attribute Indirection Register 1, see theARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionAMAIR0 c3 0 UNK 32-bit Auxiliary Memory Attribute Indirection Register 0 onpage 4-89AMAIR1 1 UNK 32-bit Auxiliary Memory Attribute Indirection Register 1 onpage 4-89CONTEXTIDR c13 0 c0 1 UNK 32-bit Process ID Register, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editiona. The reset value depends on primary inputs, CFGTE, CFGEND, and VINITHI. The value shown in Table 4-17 on page 4-15 assumes thesesignals are set to zero.b. The reset value is 0x00000000 for the Secure copy of the register. The reset value for the EAE bit of the Non-secure copy of the register is0x0. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.4.2.18 PL1 Fault handling registersTable 4-18 shows the 32-bit wide PL1 Fault handling registers.Name CRn Op1 CRm Op2 Reset DescriptionDFSR c5 0 c0 0 UNK Data Fault Status Register on page 4-75IFSR 1 UNK Instruction Fault Status Register on page 4-78Table 4-18 PL1 Fault handling registersADFSR c1 0 UNK Auxiliary Data Fault Status Register on page 4-81AIFSR 1 UNK Auxiliary Instruction Fault Status Register on page 4-82DFAR c6 0 c0 0 UNK Data Fault Address Register, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R editionIFAR 2 UNK ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R editionThe Virtualization Extensions include additional fault handling registers. For more informationsee Virtualization Extensions registers on page 4-23.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-16ID062913Non-Confidential