ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-53 ACTLR bit assignments (continued)Bits Name Function[28:27] Write streaming no-allocate threshold Write streaming no-allocate threshold:b00 12th consecutive streaming cache line does not allocate in theL1 or L2 cache. This is the reset value.b01 128th consecutive streaming cache line does not allocate in theL1 or L2 cache.b10 512th consecutive streaming cache line does not allocate in theL1 or L2 cache.b11 Disables streaming. All write-allocate lines allocate in the L1 orL2 cache.[26:25] Write streaming no L1-allocatethresholdWrite streaming no L1-allocate threshold:b00 4th consecutive streaming cache line does not allocate in the L1cache. This is the reset value.b01 64th consecutive streaming cache line does not allocate in theL1 cache.b10 128th consecutive streaming cache line does not allocate in theL1 cache.b11 Disables streaming. All write-allocate lines allocate in the L1cache.[24] Non-cacheable streaming enhancement Non-cacheable streaming enhancement. You can set this bit only if yourmemory system meets the requirement that cache line fill requests from theCortex-A15 MPCore processor are atomic.0 Disables higher performance Non-Cacheable load forwarding.This is the reset value.1 Enables higher performance Non-Cacheable load forwarding.See Non-cacheable streaming enhancement on page 6-9 formore information.[23] a Force in-order requests to the same setand wayForces in-order requests to the same set and way:0 Does not force in-order requests to the same set and way. Thisis the reset value.1 Forces in-order requests to the same set and way.[22] a Force in-order load issue Force in-order load issue:0 Does not force in-order load issue. This is the reset value.1 Forces in-order load issue.[21] a Disable L2 TLB prefetching Disables L2 TLB prefetching:0 Enables L2 TLB prefetching. This is the reset value.1 Disables L2 TLB prefetching.[20] a Disable L2 translation table walk IPAPA cache[19] a Disable L2 stage 1 translation tablewalk cacheDisables L2 translation table walk Intermediate Physical Address (IPA) toPhysical Address (PA) cache:0 Enables L2 translation table walk IPA to PA cache. This is thereset value.1 Disables L2 translation table walk IPA to PA cache.Disables L2 stage 1 translation table walk cache:0 Enables L2 stage 1 translation table walk cache. This is the resetvalue.1 Disables L2 stage 1 translation table walk cache.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-59ID062913Non-Confidential