ARM Cortex-A15 MPCore Processor Technical Reference Manual

RevisionsTable B-3 Differences between issue B and issue C (continued)Change Location AffectsRenamed PMCCFILTR to PMXEVTYPER31 in the PMUregister summary tableTable 11-1 on page 11-4r2p0Updated description for bits[3:0] of the ETMIDR ETM ID Register on page 12-20 r2p0Updated the GIC configuration section GIC configuration on page 8-6 r2p0Updated description of the nVIRQ and nVFIQ input pins Table A-4 on page A-6 r2p0Table B-4 Differences between issue C and issue DChange Location AffectsUpdated the reset value of the Main ID Register • Table 4-2 on page 4-4• Table 4-16 on page 4-14r2p1Added the reset values for MAIR0 and MAIR1 Table 4-11 on page 4-11 r2p1Updated bits[23:20] of the Main ID Register Main ID Register on page 4-27 r2p1Clarified description for bits[11:10] and bit[12] ofthe L2 Control RegisterAdded a new section for cache maintenancetransactions in the Level 2 Memory SystemchapterClarified that some memories within the L2memory system support ECC when configuredAdded a section in the L2 memory system forasynchronous errorsL2 Control Register on page 4-85Cache maintenance transactions on page 7-14Error Correction Code on page 7-4Asynchronous errors on page 7-11r2p1r2p1r2p1r2p1Updated the DBGDIDR bit assignments Table 10-2 on page 10-10 r2p1Updated the field name for bits[63:40] of theDebug Self Address Offset RegisterTable 10-16 on page 10-26r2p1Clarified description for debug registers Chapter 10 Debug r2p1Updated ARUSERS[5:0] for the read addresschannelTable A-23 on page A-19r2p1Table B-5 Differences between issue D and issue EChange Location AffectsAdded regional clock gates and processor clock stop pins asadditional configuration options• Table 1-1 on page 1-7• Implementation options on page 1-7r3p0Added description for CPUCLKOFF inputs Clocks on page 2-8 r3p0Added description for regional clock gating Regional clock gating on page 2-28 r3p0Updated the L2 Wait For Interrupt timing diagram to show thatCLKEN is asserted before the Internal L2 clock signalAdded new section for processor retention in WFI and WFElow-power stateFigure 2-13 on page 2-24Processor retention in WFI and WFElow-power state on page 2-24All revisionsr3p0ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. B-3ID062913Non-Confidential