ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-72 shows the DL1Datan bit assignments.Bits Name FunctionTable 4-72 DL1Datan bit assignments[31:0] Data Holds the data side L1 or L2 array informationTo access the DL1Datan, read or write the CP15 registers with:MRC p15, 0, , c15, c1, n; Read Data L1 Data n RegisterMCR p15, 0, , c15, c1, n; Write Data L1 Data n Registerwhere n is 0, 1, 2, or 3 for the Opcode_2 value of DL1Data0, DL1Data1, DL1Data2, orDL1Data3 Register.4.3.59 RAM Index RegisterThe RAMINDEX characteristics are:PurposeRead the instruction side L1 array contents into the IL1Datan register orread the data side L1 or L2 array contents into the DL1Datan register.Usage constraints The RAMINDEX is:• A write-only operation.• Any write to the RAMINDEX register must be followed by a DSB.• Common to the Secure and Non-secure states.• Only accessible from PL1 or higher.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-14 on page 4-13.Figure 4-42 shows the RAMINDEX bit assignments.31 24 23 22 21 18 17 0RAMIDWayIndexReservedFigure 4-42 RAMINDEX bit assignmentsARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-91ID062913Non-Confidential