ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 2 Memory System7.4 L2 cache prefetcherThe Cortex-A15 MPCore processor includes a hardware L2 auto-prefetcher. Some of the keyfeatures are:• Software-programmable prefetches on any L2 miss of 0, 2, 4, or 8 for load-store missesand 0, 1, 2, or 3 for instruction fetch misses. All prefetches are allocated into the L2 cache.• Separate mechanisms to detect and prefetch:— Load-store streams, to stride detection within a 4K page.— Instruction fetch streams, to fetch consecutive cache lines on an L2 instruction fetchmiss or an L2 cache prefetch hit.— Table walk descriptor, to fetch the consecutive cache line on an L2 table walkdescriptor miss.NoteThe prefetcher is limited to prefetch within the 4KB page of the current request.• A 16-entry prefetch request queue per processor that holds the prefetch requests generatedby either the load-store, instruction fetch, or table walk prefetchers.• A throttle mechanism to limit a maximum of six outstanding prefetch requests fromconsuming all of the shared resources that handle the data transfer to and from memory.• Support for forwarding from prefetched requests. If a read request was sent over AXIbecause of a prefetch request, and a demand access for the same line was received, theread data can be forwarded from the internal data buffers to the demand request, beforewaiting for the line to be allocated to the cache.You can program the L2 Prefetch Control Register, see L2 Prefetch Control Register onpage 4-103, to indicate the maximum number of prefetches to be allocated in the PRQ on thefollowing:• An instruction fetch miss in the L2 cache.• A load-store miss with a stride match in the L2 cache.The programmed distance is also used as the skip distance for any load-store or instruction fetchread with a stride match that hits in the L2 cache. In these cases, a single prefetch request isallocate in the PRQ as:prefetch address = current address + (stride x programmed distance)NoteThe stride for an instruction fetch access is always one cache line.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 7-9ID062913Non-Confidential