ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control31 0DataFigure 4-40 IL1Datan bit assignmentsTable 4-71 shows the IL1Datan bit assignments.Table 4-71 IL1Datan bit assignmentsBits Name Function[31:0] Data Holds the instruction side L1 array informationTo access the IL1Datan, read or write the CP15 registers with:MRC p15, 0, , c15, c0, n; Read Instruction L1 Data n RegisterMCR p15, 0, , c15, c0, n; Write Instruction L1 Data n Registerwhere n is 0, 1, or 2 for the Opcode_2 value of IL1Data0, IL1Data1, or IL1Data2 Register.4.3.58 Data L1 Data n RegisterThe DL1Datan, where n is from 0 to 3, characteristics are:PurposeHolds the data side L1 or L2 array information returned by theRAMINDEX write operation. See RAM Index Register on page 4-91 formore information.NoteBecause the data, tag and TLB arrays are greater than 32-bits wide, theprocessor contains multiple DL1Data registers, to hold the arrayinformation.Usage constraints The DL1Datan is:• A read/write register.• Common to the Secure and Non-secure states.• Only accessible from PL1 or higher.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-14 on page 4-13.Figure 4-41 shows the DL1Datan bit assignments.31 0DataFigure 4-41 DL1Datan bit assignmentsARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-90ID062913Non-Confidential