ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 2 Memory System7.6 Asynchronous errorsThe L2 memory system has two outputs that indicate asynchronous error conditions. Anasynchronous external error condition exists when either:• The nAXIERRIRQ output is asserted LOW.• The nINTERRIRQ output is asserted LOW.If an asynchronous error condition is detected, the corresponding bit in the L2 Extended ControlRegister is asserted. The asynchronous error condition can be cleared by writing 1'b0 to thecorresponding bit of the L2ECTLR. Software can only clear the L2ECTLR. Any attempt toassert the error by writing the L2ECTLR is ignored. See L2 Extended Control Register onpage 4-87 for more information.External errors on the ACE write response channel or on the ACE read data channel, associatedwith a write-allocate memory transaction, cause the nAXIERRIRQ signal to be asserted LOW.Double-bit ECC errors or invalid accesses to the internal GIC interrupt controller cause thenINTERRIRQ signal to be asserted LOW.Any external error associated with a load instruction of type ReadNoSnoop, ReadShared,ReadClean or ReadUnique is reported back to the requestor along with an error response andthis might trigger an abort.External errors associated with cache maintenance operations of type CleanShared orCleanInvalid are silently dropped..ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 7-11ID062913Non-Confidential