ARM Cortex-A15 MPCore Processor Technical Reference Manual

Performance Monitor UnitTable 11-4 Common Event Identification Register 0 bit assignments (continued)Bit Event number Event implemented if set to 1 or not implemented if set to 0[2] 0x02 Level 1 instruction TLB refill. This event is implemented.[1] 0x01 Level 1 instruction cache refill. This event is implemented.[0] 0x00 Instruction architecturally executed, condition check pass, software increment. This bit is RAO.11.4.4 Performance Monitor Common Event Identification Register 1PMCEID1 is reserved, so this register is always RAZ.11.4.5 Peripheral Identification RegistersThe Peripheral Identification Registers provide standard information required for allcomponents that conform to the ARM PMUv2 architecture. They are a set of eight registers,listed in register number order in Table 11-5. These registers are Performance Monitors registersthat are visible only in the memory-mapped views of the Performance Monitors registers.Table 11-5 Summary of the Peripheral Identification RegistersRegister Value OffsetPeripheral ID4 0x04 0xFD0Peripheral ID5 0x00 0xFD4Peripheral ID6 0x00 0xFD8Peripheral ID7 0x00 0xFDCPeripheral ID0 0xAF 0xFE0Peripheral ID1 0xB9 0xFE4Peripheral ID2 0x3B 0xFE8Peripheral ID3 0x00 0xFECOnly bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, theeight Peripheral ID Registers define a single 64-bit Peripheral ID.The ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition describes theseregisters.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 11-12ID062913Non-Confidential