ARM Cortex-A15 MPCore Processor Technical Reference Manual

Signal DescriptionsA.9 AXI interfacesFor descriptions of AXI interface signals, see the AMBA AXI Protocol Specification. In thissection, the suffix M in the signal name signifies an AXI master interface signal and the suffixS signifies an AXI slave interface signal.This section describes the AXI interfaces in:• AXI master interface signals.• ACP signals on page A-17.A.9.1AXI master interface signalsThe following sections describe the AXI master interface signals:• Clock and configuration signals.• Asynchronous error signals on page A-13.• Write address channel signals on page A-14.• Write data channel signals on page A-14.• Write response channel signals on page A-15.• Read address channel signals on page A-15.• Read data channel signals on page A-15.• Snoop address channel signals on page A-16.• Snoop data channel signals on page A-16.• Snoop response channel signals on page A-16.• Read/write acknowledge signals on page A-17.Clock and configuration signalsTable A-8 shows the clock and configuration signals for the AXI master interface.Signal Type DescriptionTable A-8 Clock and configuration signalsACLKENM Input AXI master bus clock enable. See Clocking and resets on page 2-8 for moreinformation.ACINACTM Input Snoop interface is inactive and no longer accepting requests.A64n128M Input Selects 64-bit or 128-bit AXI bus width:0 128-bit bus width.1 64-bit bus width.BROADCASTCACHEMAINT Input Enable broadcasting of cache maintenance operations to downstream caches:0 Cache maintenance operations are not broadcasted to downstreamcaches.1 Cache maintenance operations are broadcasted to downstream caches.This signal is only sampled during reset of the processor. See ACE configurations onpage 7-15 for more information.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. A-12ID062913Non-Confidential