ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlName CRn Op1 CRm Op2 Reset DescriptionTable 4-16 Identification registers (continued)ID_MMFR2 6 0x01240000 Memory Model Feature Register 2 on page 4-37ID_MMFR3 7 0x02102211 Memory Model Feature Register 3 on page 4-38ID_ISAR0 c2 0 0x02101110 Instruction Set Attribute Register 0 on page 4-40ID_ISAR1 1 0x13112111 Instruction Set Attribute Register 1 on page 4-41ID_ISAR2 2 0x21232041 Instruction Set Attribute Register 2 on page 4-43ID_ISAR3 3 0x11112131 Instruction Set Attribute Register 3 on page 4-44ID_ISAR4 4 0x10011142 Instruction Set Attribute Register 4 on page 4-46ID_ISAR5 5 0x00000000 Instruction Set Attribute Register 5 on page 4-48CCSIDR 1 c0 0 UNK Cache Size ID Register on page 4-48CLIDR 1 0x0A200023 Cache Level ID Register on page 4-50AIDR 7 0x00000000 Auxiliary ID Register on page 4-51CSSELR 2 c0 0 UNK Cache Size Selection Register on page 4-51a. The reset value depends on the primary input, IMINLN. The value shown in Table 4-16 on page 4-14 assumes IMINLN is setto 1.b. The reset value depends on the primary input, CLUSTERID, and the number of configured processors in the MPCore device.4.2.17 Virtual memory control registersTable 4-17 shows the Virtual memory control registers.Name CRn Op1 CRm Op2 Reset Width DescriptionTable 4-17 Virtual memory registersSCTLR c1 0 c0 0 0x00C50078 a 32-bit System Control Register on page 4-54TTBR0 c2 0 c0 0 UNK 32-bit Translation Table Base Register 0 and Register 1 onpage 4-74- 0 c2 - 64-bit Translation Table Base Register 0 and Register 1 onpage 4-74TTBR1 c2 0 c0 1 UNK 32-bit Translation Table Base Register 0 and Register 1 onpage 4-74- 1 c2 - 64-bit Translation Table Base Register 0 and Register 1 onpage 4-74TTBCR c2 0 c0 2 0x00000000 b 32-bit Translation Table Base Control Register on page 4-74DACR c3 0 c0 0 UNK 32-bit Domain Access Control Register, see the ARM ®Architecture Reference Manual ARMv7-A andARMv7-R editionPRRR c10 0 c2 0 0x00098AA4 32-bit Primary Region Remap Register, see the ARM ®Architecture Reference Manual ARMv7-A andARMv7-R editionARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-15ID062913Non-Confidential