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ARM Cortex-A15 MPCore Processor Technical Reference Manual

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Program Trace Macrocell12.7.8 Configuration Code Extension RegisterThe ETMCCER characteristics are:PurposeHolds the PTM configuration information additional to that in theETMCCR. See Configuration Code Register on page 12-16.Usage constraints Software uses this register with the ETMCCR.ConfigurationsAvailable in all PTM configurations.Attributes See the register summary in Table 12-4 on page 12-11.Figure 12-8 shows the ETMCCER bit assignments.31 30 29 28 27 26 25 24 23 22 2116 15 13 12 11 10 3 2 0RAZ RAZ1 1Extended externalinput bus sizeTimestamp sizeTimestamp encodingReduced function counterVirtualization ExtensionsimplementedGenerate timestamps forDMB and DSB operationsDMB and DSB are waypointsReturn stack implementedTimestamping implementedNumber of extendedexternal input selectorsAll registers readableRAONumber of instrumentation resourcesFigure 12-8 ETMCCER bit assignmentsTable 12-11 shows the ETMCCER bit assignments.Table 12-11 ETMCCER bit assignmentsBits Name Function[31:30] - SBZP.[29] Timestamp size The timestamp size is 64 bits. For the <strong>Cortex</strong>-<strong>A15</strong> <strong>MPCore</strong>processor, this value is 1.[28] Timestamp encoding Specifies that timestamp is encoded as a natural binary number. Forthe <strong>Cortex</strong>-<strong>A15</strong> <strong>MPCore</strong> processor, this value is 1.[27] Reduced function counter Specifies that all counters are implemented as full function counters.For the <strong>Cortex</strong>-<strong>A15</strong> <strong>MPCore</strong> processor, this value is 0.[26] Virtualization Extensions implemented Specifies that Virtualization Extensions are implemented. For the<strong>Cortex</strong>-<strong>A15</strong> <strong>MPCore</strong> processor, this value is 1.[25] Generate timestamp for DMB and DSB operations Timestamps are not generated for DMB and DSB operations. For the<strong>Cortex</strong>-<strong>A15</strong> <strong>MPCore</strong> processor, this value is 0.[24] DMB and DSB are waypoints DMB and DSB instructions are not treated as waypoints. For the<strong>Cortex</strong>-<strong>A15</strong> <strong>MPCore</strong> processor, this value is 0.[23] Return stack implemented Specifies that return stack is implemented. For the <strong>Cortex</strong>-<strong>A15</strong><strong>MPCore</strong> processor, this value is 1.<strong>ARM</strong> DDI 0438I Copyright © 2011-2013 <strong>ARM</strong>. All rights reserved. 12-21ID062913Non-Confidential

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