ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 2 Memory System7.2 Cache organizationThe L2 cache is 16-way set-associative of configurable size. The cache is physically-addressed.The cache sizes are configurable with sizes of 512KB, 1MB, 2MB, and 4MB.You can configure the L2 memory system pipeline to insert wait states to take into account thelatencies of the compiled memories for the implementation of the RAMs.The L2 cache incorporates a single dirty bit per cache line. A write to a cache line results in theline being written back to memory after the line is evicted from the L2 cache.This section describes cache organization in:• L2 cache bank structure.• Strictly-enforced inclusion property with L1 data caches on page 7-4.• Enabling and disabling the L2 cache on page 7-4.• Error Correction Code on page 7-4.• Register slice support for large cache sizes on page 7-5.7.2.1 L2 cache bank structureThe L2 cache is partitioned into multiple banks to enable parallel operations. The followinglevels of banking exist:• The tag array is partitioned into multiple banks to enable up to four requests to accessdifferent tag banks of the L2 cache simultaneously.• Each tag bank is partitioned into multiple data banks to enable streaming accesses to thedata banks. Each tag bank consists of four data banks.Figure 7-1 shows the logical representation of an L2 cache bank structure with a configurationof all possible tag and data bank combinations.Tag bank selected by PA [7:6]Data bank selected by PA [5:4]Data bank 0Data bank 0Tag bank 0 requestsData bank 1Data bank 2Tag bank 1 requestsData bank 1Data bank 2Data bank 3Data bank 3Tag bank 0Tag bank 1Data bank 0Data bank 0Tag bank 2 requestsData bank 1Data bank 2Tag bank 3 requestsData bank 1Data bank 2Data bank 3Data bank 3Tag bank 2Tag bank 3Figure 7-1 L2 cache bank structureARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 7-3ID062913Non-Confidential