ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-35 shows the ID_PFR1 bit assignments.Table 4-35 ID_PFR1 bit assignmentsBits Name Function[31:20] - Reserved, RAZ.[19:16] Generic Timer Indicates support for Generic Timer Extension:0x1Processor supports Generic Timer Extension.[15:12] Virtualization Extensions Indicates support for Virtualization Extensions:0x1Processor supports Virtualization Extensions.[11:8] M profile programmers model Indicates support for microcontroller programmers model:0x0Processor does not support microcontroller programmers model.[7:4] Security Extensions Indicates support for Security Extensions. This includes support for Monitor mode andthe SMC instruction:0x1Processor supports Security Extensions.[3:0] Programmers model Indicates support for the standard programmers model for ARMv4 and later. Modelmust support User, FIQ, IRQ, Supervisor, Abort, Undefined and System modes:0x1Processor supports the standard programmers model for ARMv4 andlater.To access the ID_PFR1, read the CP15 register with:MRC p15, 0, , c0, c1, 1 ; Read Processor Feature Register 14.3.9 Debug Feature Register 0The ID_DFR0 characteristics are:PurposeProvides top-level information about the debug system.Usage constraints The ID_DFR0 is:• A read-only register.• Common to the Secure and Non-secure states.• Only accessible from PL1 or higher.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-2 on page 4-4.Figure 4-8 shows the ID_DFR0 bit assignments.31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0ReservedPerformance Monitors ExtensionDebug model, M profileMemory-mapped trace modelCoprocessor trace modelMemory-mapped debug modelCoprocessor Secure debug modelCoprocessor debug modelFigure 4-8 ID_DFR0 bit assignmentsARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-33ID062913Non-Confidential