ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 1 Memory SystemIt is UNPREDICTABLE whether memory requests for pages that are marked as InnerNon-Shareable are coherent with the Cortex-A15 MPCore processor. No code must assume thatNon-Shareable pages are incoherent among the caches.The L1 data cache implements a MESI coherence protocol.6.4.3 Cache disabled behaviorWhen you clear the C bit in the CP15 System Control Register for a given processor, see SystemControl Register on page 4-54, data caching is disabled and no new cache lines are allocated tothe L1 data cache and L2 cache because of requests from that processor. This is important whencleaning and invalidating the caches for power down. Cache lines can be allocated frommemory requests of other processors, unless their cache enable bits are also cleared. The effecton the L1 memory system is that all Write-Back Read-Write-Allocate pages are treated asWrite-Back No-Allocate pages.When you disable the cache, all Write-Back Cacheable requests still look up the L1 cache. Ifthere is a cache hit, the cache is read or updated in the same way as if the cache is enabled. Thisenables Cacheable memory to remain fully coherent while the cache is disabled.While the cache is disabled, it remains fully coherent with the L2 cache and the other L1 datacaches.6.4.4 Non-cacheable streaming enhancementYou can enable the ACTLR[24], Non-cacheable streaming enhancement bit, only if yourmemory system meets the requirement that cache line fill requests from the Cortex-A15MPCore processor are atomic. Specifically, if the Cortex-A15 MPCore processor requests acache line fill on the AXI master read address channel, any given write request from a differentmaster is ordered completely before or after the cache line fill read. This means that after thememory read for the cache line fill has started, writes from any other master to the same cacheline are stalled until that memory read is completed. Setting this bit enables higher performancefor applications with streaming reads from memory types that do not allocate into the cache.Because it is possible to build an AXI interconnect that does not comply with the specifiedrequirement, the ACTLR[24] bit defaults to disabled.6.4.5 Synchronization primitivesThe L1 memory system supports the ARMv7-A Load-Exclusive, Store-Exclusive, andClear-Exclusive synchronization primitive instructions. For all nonshareable memory pages, thesynchronization primitives are supported with a local monitor that is in each L1 memory system.For shareable memory pages, the local monitor is used in conjunction with a global monitor.Where the global monitor resides depends on the memory type and cacheability.Internal coherent global monitorIf synchronization primitives are used for memory pages that are shareable Normal Write-Backand the cache is enabled, SCTLR.C is 1, the external monitor on AXI is not used. Instead, theglobal monitor function is handled in the L1 and L2 memory system using the cache coherenceinformation.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 6-9ID062913Non-Confidential