ARM Cortex-A15 MPCore Processor Technical Reference Manual

Functional DescriptionL2 Wait for InterruptWhen all the processors are in WFI low-power state, the shared L2 memory system logic that iscommon to all the processors can also enter a WFI low-power state. In L2 WFI low-power state,all internal clocks in the processor are disabled, with the exception of the asynchronous DebugPCLKDBG domain.Entry into L2 WFI low-power state can only occur if specific requirements are met and thefollowing sequence applied:• All processors are in WFI low-power state and therefore, all the processorsSTANDBYWFI outputs are asserted. Assertion of all the processors STANDBYWFIoutputs guarantee that all the processors are in idle and low power state. All clocks in theprocessor, with the exception of a small amount of clock wake up logic, are disabled.• The SoC asserts the input pin ACINACTM after all responses are received and before itsends any new transactions on the AXI master interface. This prevents the L2 memorysystem from accepting any new requests from the AXI master interface and ensures thatall outstanding transactions are complete. If the SoC asserts ACVALIDM whileACINACTM is asserted, then ACINACTM must be deasserted for the request to beaccepted.• The SoC asserts the input pin AINACTS after all responses are received and before itsends any new transactions on the ACP slave interface. This prevents the L2 memorysystem from accepting any new requests from the ACP slave interface and ensures that alloutstanding transactions are complete. If the SoC asserts ARVALIDS, AWVALIDS, orWVALIDS while AINACTS is asserted, then AINACTS must be deasserted for therequest to be accepted.• When the L2 memory system completed the outstanding transactions for AXI interfaces,it can then enter the low power state, that is, L2 WFI low-power state. On entry into L2WFI low-power state, STANDBYWFIL2 is asserted. Assertion of STANDBYWFIL2guarantees that the L2 is in idle and does not accept any new transactions.• The SoC can then deassert the CLKEN input to the Cortex-A15 MPCore processor tostop all remaining internal clocks within the Cortex-A15 MPCore processor that arederived from CLK. All clocks in the shared L2 memory system logic, Interrupt Controllerand Timer, are disabled.The SoC must assert the CLKEN input on a WFI wake up event to enable the L2 memorysystem and potentially the processor. There are two classes of wake up events:• An event that requires only the L2 memory system to be enabled.• An event that requires both the L2 memory and the processor to be enabled.The following wake up events cause the L2 memory system and the processor to exit WFIlow-power state:• A physical IRQ or FIQ interrupt.• A debug event.• Powerup or soft reset.Wake up events that only require the L2 memory system to exit WFI low-power state include:• Deassertion of ACINACTM to service an external snoop request on the AC channelinterface.• Deassertion of AINACTS to service an ACP transaction on the slave interface.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 2-23ID062913Non-Confidential