ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-2 on page 4-4.Figure 4-20 shows the CSSELR bit assignments.31 4 3 1 0UNK/SBZPLevelInDFigure 4-20 CSSELR bit assignmentsTable 4-49 shows the CSSELR bit assignments.Table 4-49 CSSELR bit assignmentsBits Name Function[31:4] - Reserved, UNK/SBZP[3:1] Level Cache level of required cache:b000 Level 1.b001 Level 2.b010-b111 Reserved.[0] InD Instruction not Data bit:0 Data or unified cache.1 Instruction cache.To access the CSSELR, read or write the CP15 register with:MRC p15, 2, , c0, c0, 0; Read Cache Size Selection RegisterMCR p15, 2, , c0, c0, 0; Write Cache Size Selection Register4.3.25 Virtualization Processor ID RegisterThe VPIDR characteristics are:PurposeHolds the value of the Virtualization Processor ID. A Non-secure read ofthe MIDR from PL1 returns the value of this register.Usage constraints The VPIDR is:• A read/write register.• Only accessible from Hyp mode or from Monitor mode whenSCR.NS is 1.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-2 on page 4-4.Figure 4-21 on page 4-53 shows the VPIDR bit assignments.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-52ID062913Non-Confidential