ARM Cortex-A15 MPCore Processor Technical Reference Manual

RevisionsTable B-7 Differences between issue F and issue GChange Location AffectsClarified description for CLKEN Clocks on page 2-8 r3p2Updated the reset sequence for a full soft reset on theprocessorSoft reset on page 2-17r3p2Updated information on L2 Wait for Interrupt L2 Wait for Interrupt on page 2-23 r3p2Updated the reset value of the Main ID Register • Table 4-2 on page 4-4• Table 4-16 on page 4-14r3p2Updated bits[23:20] of the Main ID Register Main ID Register on page 4-27 r3p2Corrected description for bits[26:25] of the AuxiliaryControl RegisterUpdated text for the MAIR0, MAIR1, AMAIR0, AMAIR1,HAMAIR0, and HAMAIR1 registersAuxiliary Control Register on page 4-57• Memory Attribute IndirectionRegister 0 on page 4-88• Memory Attribute IndirectionRegister 1 on page 4-89• Auxiliary Memory AttributeIndirection Register 0 on page 4-89• Auxiliary Memory AttributeIndirection Register 1 on page 4-89• Hyp Auxiliary Memory AttributeIndirection Register 0 on page 4-89• Hyp Auxiliary Memory AttributeIndirection Register 1 on page 4-89All revisionsAll revisionsClarified information about intermediate table walk caches Intermediate table walk caches on page 5-8 All revisionsUpdated description for instruction cache speculativememory accessesInstruction cache speculative memoryaccesses on page 6-4r3p2Clarified information about external memory errors Asynchronous errors on page 7-11 All revisionsAdded Debug Device ID Register 1 Debug Device ID Register 1 on page 10-30 r3p2Added event mnemonic column to the PMU events table Table 11-7 on page 11-15 All revisionsTable B-8 Differences between issue G and issue HChange Location AffectsUpdated description for the CPUCLKOFF pins Clocks on page 2-8 All revisionsUpdated description in the L2 Wait for Interrupt section L2 Wait for Interrupt on page 2-23 All revisionsUpdated the NEON and VFP power domain section NEON and VFP power domain on page 2-32 All revisionsUpdated the sequence when the Cortex-A15 MPCoreprocessor enters Dormant modeCombined the ThumbEE architecture section with the JazelleExtension section from Chapter 3 Programmers Model intoone section called Execution environment supportDormant mode on page 2-35Execution environment support on page 3-3All revisionsAll revisionsUpdated the reset value of the Main ID Register • Table 4-2 on page 4-4• Table 4-16 on page 4-14r3p3ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. B-5ID062913Non-Confidential