ARM Cortex-A15 MPCore Processor Technical Reference Manual

Preface(continued)Stylemonospace boldSMALL CAPITALSPurposeDenotes language keywords when used outside example code.Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example:MRC p15, 0 , , , Used in body text for a few terms that have specific technical meanings, that are defined in the ARM ® Glossary.For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE.Timing diagramsKey to timing diagram conventions explains the components used in these diagrams. Whenvariations occur they have clear labels. You must not assume any timing information that is notexplicit in the diagrams.Shaded bus and signal areas are undefined, so the bus or signal can assume any value within theshaded area at that time. The actual level is unimportant and does not affect normal operation.ClockHIGH to LOWTransientHIGH/LOW to HIGHBus stableBus to high impedanceBus changeHigh impedance to stable busKey to timing diagram conventionsTiming diagrams sometimes show single-bit signals as HIGH and LOW at the same time andthey look similar to the bus change shown in Key to timing diagram conventions. If a timingdiagram shows a single-bit signal in this way then its value does not affect the accompanyingdescription.SignalsThe signal conventions are:Signal levelLower-case nThe level of an asserted signal depends on whether the signal isactive-HIGH or active-LOW. Asserted means:• HIGH for active-HIGH signals.• LOW for active-LOW signals.At the start or end of a signal name denotes an active-LOW signal.Additional readingThis section lists relevant documents published by third parties.See Infocenter, http://infocenter.arm.com, for access to ARM documentation.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. ixID062913Non-Confidential