ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control4.3.12 Memory Model Feature Register 1The ID_MMFR1 characteristics are:PurposeProvides information about the implemented memory model and memorymanagement support.Usage constraints The ID_MMFR1 is:• A read-only register.• Common to the Secure and Non-secure states.• Only accessible from PL1 or higher.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-2 on page 4-4.Figure 4-10 shows the ID_MMFR1 bit assignments.31 28 27 2423 20 19 16 15 12 11 8 7 4 3 0Branch predictorL1 cache test and cleanL1 unified cacheL1 Harvard cacheL1 unified cache set/wayL1 Harvard cache set/wayL1 unified cache VAL1 Harvard cache VATable 4-38 shows the ID_MMFR1 bit assignments.Figure 4-10 ID_MMFR1 bit assignmentsTable 4-38 ID_MMFR1 bit assignmentsBits Name Function[31:28] Branch predictor Indicates branch predictor management requirements.0x2Branch predictor requires flushing on:• Enabling or disabling the MMU.• Writing new data to instruction locations.• Writing new mappings to the translation tables.• Any change to the TTBR0, TTBR1, or TTBCR registers without acorresponding change to the FCSE ProcessID or ContextID.[27:24] L1 cache test and clean Indicates the supported L1 data cache test and clean operations, for Harvard or unified cacheimplementation:0x0Not supported.[23:20] L1 unified cache Indicates the supported entire L1 cache maintenance operations, for a unified cacheimplementation:0x0Not supported.[19:16] L1 Harvard cache Indicates the supported entire L1 cache maintenance operations, for a Harvard cacheimplementation:0x0Not supported.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-36ID062913Non-Confidential